1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * Matrix-centric header file for the AT91SAM9M1x family 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * Copyright (C) 2008 Atmel Corporation. 5*af930827SMasahiro Yamada * 6*af930827SMasahiro Yamada * Memory Controllers (MATRIX, EBI) - System peripherals registers. 7*af930827SMasahiro Yamada * Based on AT91SAM9G45 preliminary datasheet. 8*af930827SMasahiro Yamada * 9*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 10*af930827SMasahiro Yamada */ 11*af930827SMasahiro Yamada 12*af930827SMasahiro Yamada #ifndef AT91SAM9G45_MATRIX_H 13*af930827SMasahiro Yamada #define AT91SAM9G45_MATRIX_H 14*af930827SMasahiro Yamada 15*af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 16*af930827SMasahiro Yamada 17*af930827SMasahiro Yamada struct at91_matrix { 18*af930827SMasahiro Yamada u32 mcfg[16]; 19*af930827SMasahiro Yamada u32 scfg[16]; 20*af930827SMasahiro Yamada u32 pras[16][2]; 21*af930827SMasahiro Yamada u32 mrcr; /* 0x100 Master Remap Control */ 22*af930827SMasahiro Yamada u32 filler[3]; 23*af930827SMasahiro Yamada u32 tcmr; 24*af930827SMasahiro Yamada u32 filler2; 25*af930827SMasahiro Yamada u32 ddrmpr; 26*af930827SMasahiro Yamada u32 filler3[3]; 27*af930827SMasahiro Yamada u32 ebicsa; 28*af930827SMasahiro Yamada u32 filler4[47]; 29*af930827SMasahiro Yamada u32 wpmr; 30*af930827SMasahiro Yamada u32 wpsr; 31*af930827SMasahiro Yamada }; 32*af930827SMasahiro Yamada 33*af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 34*af930827SMasahiro Yamada 35*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 36*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 37*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_FOUR (2 << 0) 38*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 39*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 40*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) 41*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 42*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_128 (7 << 0) 43*af930827SMasahiro Yamada 44*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 45*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 46*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 47*af930827SMasahiro Yamada #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 48*af930827SMasahiro Yamada 49*af930827SMasahiro Yamada #define AT91_MATRIX_M0PR_SHIFT 0 50*af930827SMasahiro Yamada #define AT91_MATRIX_M1PR_SHIFT 4 51*af930827SMasahiro Yamada #define AT91_MATRIX_M2PR_SHIFT 8 52*af930827SMasahiro Yamada #define AT91_MATRIX_M3PR_SHIFT 12 53*af930827SMasahiro Yamada #define AT91_MATRIX_M4PR_SHIFT 16 54*af930827SMasahiro Yamada #define AT91_MATRIX_M5PR_SHIFT 20 55*af930827SMasahiro Yamada #define AT91_MATRIX_M6PR_SHIFT 24 56*af930827SMasahiro Yamada #define AT91_MATRIX_M7PR_SHIFT 28 57*af930827SMasahiro Yamada 58*af930827SMasahiro Yamada #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ 59*af930827SMasahiro Yamada #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ 60*af930827SMasahiro Yamada #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ 61*af930827SMasahiro Yamada #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ 62*af930827SMasahiro Yamada 63*af930827SMasahiro Yamada #define AT91_MATRIX_RCB0 (1 << 0) 64*af930827SMasahiro Yamada #define AT91_MATRIX_RCB1 (1 << 1) 65*af930827SMasahiro Yamada #define AT91_MATRIX_RCB2 (1 << 2) 66*af930827SMasahiro Yamada #define AT91_MATRIX_RCB3 (1 << 3) 67*af930827SMasahiro Yamada #define AT91_MATRIX_RCB4 (1 << 4) 68*af930827SMasahiro Yamada #define AT91_MATRIX_RCB5 (1 << 5) 69*af930827SMasahiro Yamada #define AT91_MATRIX_RCB6 (1 << 6) 70*af930827SMasahiro Yamada #define AT91_MATRIX_RCB7 (1 << 7) 71*af930827SMasahiro Yamada #define AT91_MATRIX_RCB8 (1 << 8) 72*af930827SMasahiro Yamada #define AT91_MATRIX_RCB9 (1 << 9) 73*af930827SMasahiro Yamada #define AT91_MATRIX_RCB10 (1 << 10) 74*af930827SMasahiro Yamada 75*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 76*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 77*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) 78*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 79*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) 80*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) 81*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) 82*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) 83*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) 84*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) 85*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) 86*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) 87*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) 88*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) 89*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) 90*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) 91*af930827SMasahiro Yamada 92*af930827SMasahiro Yamada #endif 93