1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h] 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * Copyright (C) 2007 Atmel Corporation. 5*af930827SMasahiro Yamada * 6*af930827SMasahiro Yamada * Memory Controllers (MATRIX, EBI) - System peripherals registers. 7*af930827SMasahiro Yamada * Based on AT91SAM9260 datasheet revision B. 8*af930827SMasahiro Yamada * 9*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 10*af930827SMasahiro Yamada */ 11*af930827SMasahiro Yamada 12*af930827SMasahiro Yamada #ifndef AT91SAM9260_MATRIX_H 13*af930827SMasahiro Yamada #define AT91SAM9260_MATRIX_H 14*af930827SMasahiro Yamada 15*af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 16*af930827SMasahiro Yamada 17*af930827SMasahiro Yamada /* 18*af930827SMasahiro Yamada * This struct defines access to the matrix' maximum of 19*af930827SMasahiro Yamada * 16 masters and 16 slaves. 20*af930827SMasahiro Yamada * However, on the AT91SAM9260/9G20/9XE there exist only 21*af930827SMasahiro Yamada * 6 Masters and 5 Slaves! 22*af930827SMasahiro Yamada */ 23*af930827SMasahiro Yamada struct at91_matrix { 24*af930827SMasahiro Yamada u32 mcfg[16]; /* Master Configuration Registers */ 25*af930827SMasahiro Yamada u32 scfg[16]; /* Slave Configuration Registers */ 26*af930827SMasahiro Yamada u32 pras[16][2]; /* Priority Assignment Slave Registers */ 27*af930827SMasahiro Yamada u32 mrcr; /* Master Remap Control Register */ 28*af930827SMasahiro Yamada u32 filler[0x06]; 29*af930827SMasahiro Yamada u32 ebicsa; /* EBI Chip Select Assignment Register */ 30*af930827SMasahiro Yamada }; 31*af930827SMasahiro Yamada 32*af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 33*af930827SMasahiro Yamada 34*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 35*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 36*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_FOUR (2 << 0) 37*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 38*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 39*af930827SMasahiro Yamada 40*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 41*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 42*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 43*af930827SMasahiro Yamada #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 44*af930827SMasahiro Yamada #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 45*af930827SMasahiro Yamada #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 46*af930827SMasahiro Yamada 47*af930827SMasahiro Yamada #define AT91_MATRIX_M0PR_SHIFT 0 48*af930827SMasahiro Yamada #define AT91_MATRIX_M1PR_SHIFT 4 49*af930827SMasahiro Yamada #define AT91_MATRIX_M2PR_SHIFT 8 50*af930827SMasahiro Yamada #define AT91_MATRIX_M3PR_SHIFT 12 51*af930827SMasahiro Yamada #define AT91_MATRIX_M4PR_SHIFT 16 52*af930827SMasahiro Yamada #define AT91_MATRIX_M5PR_SHIFT 20 53*af930827SMasahiro Yamada 54*af930827SMasahiro Yamada #define AT91_MATRIX_RCB0 (1 << 0) 55*af930827SMasahiro Yamada #define AT91_MATRIX_RCB1 (1 << 1) 56*af930827SMasahiro Yamada 57*af930827SMasahiro Yamada #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 58*af930827SMasahiro Yamada #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) 59*af930827SMasahiro Yamada #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) 60*af930827SMasahiro Yamada #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 61*af930827SMasahiro Yamada #define AT91_MATRIX_DBPUC (1 << 8) 62*af930827SMasahiro Yamada #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) 63*af930827SMasahiro Yamada #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) 64*af930827SMasahiro Yamada #define AT91_MATRIX_EBI_IOSR_SEL (1 << 17) 65*af930827SMasahiro Yamada 66*af930827SMasahiro Yamada /* Maximum Number of Allowed Cycles for a Burst */ 67*af930827SMasahiro Yamada #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) 68*af930827SMasahiro Yamada #define AT91_MATRIX_SLOT_CYCLE_(x) (x << 0) 69*af930827SMasahiro Yamada 70*af930827SMasahiro Yamada #endif 71