1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * Copyright (C) 2007 Andrew Victor 5*af930827SMasahiro Yamada * Copyright (C) 2007 Atmel Corporation. 6*af930827SMasahiro Yamada * 7*af930827SMasahiro Yamada * Reset Controller (RSTC) - System peripherals regsters. 8*af930827SMasahiro Yamada * Based on AT91SAM9261 datasheet revision D. 9*af930827SMasahiro Yamada * 10*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 11*af930827SMasahiro Yamada */ 12*af930827SMasahiro Yamada 13*af930827SMasahiro Yamada #ifndef AT91_RSTC_H 14*af930827SMasahiro Yamada #define AT91_RSTC_H 15*af930827SMasahiro Yamada 16*af930827SMasahiro Yamada /* Reset Controller Status Register */ 17*af930827SMasahiro Yamada #define AT91_ASM_RSTC_SR (ATMEL_BASE_RSTC + 0x04) 18*af930827SMasahiro Yamada #define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08) 19*af930827SMasahiro Yamada 20*af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 21*af930827SMasahiro Yamada 22*af930827SMasahiro Yamada typedef struct at91_rstc { 23*af930827SMasahiro Yamada u32 cr; /* Reset Controller Control Register */ 24*af930827SMasahiro Yamada u32 sr; /* Reset Controller Status Register */ 25*af930827SMasahiro Yamada u32 mr; /* Reset Controller Mode Register */ 26*af930827SMasahiro Yamada } at91_rstc_t; 27*af930827SMasahiro Yamada 28*af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 29*af930827SMasahiro Yamada 30*af930827SMasahiro Yamada #define AT91_RSTC_KEY 0xA5000000 31*af930827SMasahiro Yamada 32*af930827SMasahiro Yamada #define AT91_RSTC_CR_PROCRST 0x00000001 33*af930827SMasahiro Yamada #define AT91_RSTC_CR_PERRST 0x00000004 34*af930827SMasahiro Yamada #define AT91_RSTC_CR_EXTRST 0x00000008 35*af930827SMasahiro Yamada 36*af930827SMasahiro Yamada #define AT91_RSTC_MR_URSTEN 0x00000001 37*af930827SMasahiro Yamada #define AT91_RSTC_MR_URSTIEN 0x00000010 38*af930827SMasahiro Yamada #define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) 39*af930827SMasahiro Yamada #define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 40*af930827SMasahiro Yamada 41*af930827SMasahiro Yamada #define AT91_RSTC_SR_NRSTL 0x00010000 42*af930827SMasahiro Yamada 43*af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ 44*af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) 45*af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) 46*af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) 47*af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) 48*af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_USER (4 << 8) 49*af930827SMasahiro Yamada 50*af930827SMasahiro Yamada #endif 51