1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * Copyright (C) 2010 3*af930827SMasahiro Yamada * Reinhard Meyer, reinhard.meyer@emk-elektronik.de 4*af930827SMasahiro Yamada * 5*af930827SMasahiro Yamada * Enhanced Embedded Flash Controller 6*af930827SMasahiro Yamada * Based on AT91SAM9XE datasheet 7*af930827SMasahiro Yamada * 8*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 9*af930827SMasahiro Yamada */ 10*af930827SMasahiro Yamada 11*af930827SMasahiro Yamada #ifndef AT91_EEFC_H 12*af930827SMasahiro Yamada #define AT91_EEFC_H 13*af930827SMasahiro Yamada 14*af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 15*af930827SMasahiro Yamada 16*af930827SMasahiro Yamada typedef struct at91_eefc { 17*af930827SMasahiro Yamada u32 fmr; /* Flash Mode Register RW */ 18*af930827SMasahiro Yamada u32 fcr; /* Flash Command Register WO */ 19*af930827SMasahiro Yamada u32 fsr; /* Flash Status Register RO */ 20*af930827SMasahiro Yamada u32 frr; /* Flash Result Register RO */ 21*af930827SMasahiro Yamada } at91_eefc_t; 22*af930827SMasahiro Yamada 23*af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 24*af930827SMasahiro Yamada 25*af930827SMasahiro Yamada #define AT91_EEFC_FMR_FWS_MASK 0x00000f00 26*af930827SMasahiro Yamada #define AT91_EEFC_FMR_FRDY_BIT 0x00000001 27*af930827SMasahiro Yamada 28*af930827SMasahiro Yamada #define AT91_EEFC_FCR_KEY 0x5a000000 29*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FARG_MASK 0x00ffff00 30*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FARG_SHIFT 8 31*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_GETD 0x0 32*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_WP 0x1 33*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_WPL 0x2 34*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_EWP 0x3 35*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_EWPL 0x4 36*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_EA 0x5 37*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_SLB 0x8 38*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_CLB 0x9 39*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_GLB 0xA 40*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_SGPB 0xB 41*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_CGPB 0xC 42*af930827SMasahiro Yamada #define AT91_EEFC_FCR_FCMD_GGPB 0xD 43*af930827SMasahiro Yamada 44*af930827SMasahiro Yamada #define AT91_EEFC_FSR_FRDY 1 45*af930827SMasahiro Yamada #define AT91_EEFC_FSR_FCMDE 2 46*af930827SMasahiro Yamada #define AT91_EEFC_FSR_FLOCKE 4 47*af930827SMasahiro Yamada 48*af930827SMasahiro Yamada #endif 49