1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * Copyright (C) 2010 3*af930827SMasahiro Yamada * Reinhard Meyer, reinhard.meyer@emk-elektronik.de 4*af930827SMasahiro Yamada * 5*af930827SMasahiro Yamada * Debug Unit 6*af930827SMasahiro Yamada * Based on AT91SAM9XE datasheet 7*af930827SMasahiro Yamada * 8*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 9*af930827SMasahiro Yamada */ 10*af930827SMasahiro Yamada 11*af930827SMasahiro Yamada #ifndef AT91_DBU_H 12*af930827SMasahiro Yamada #define AT91_DBU_H 13*af930827SMasahiro Yamada 14*af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 15*af930827SMasahiro Yamada 16*af930827SMasahiro Yamada typedef struct at91_dbu { 17*af930827SMasahiro Yamada u32 cr; /* Control Register WO */ 18*af930827SMasahiro Yamada u32 mr; /* Mode Register RW */ 19*af930827SMasahiro Yamada u32 ier; /* Interrupt Enable Register WO */ 20*af930827SMasahiro Yamada u32 idr; /* Interrupt Disable Register WO */ 21*af930827SMasahiro Yamada u32 imr; /* Interrupt Mask Register RO */ 22*af930827SMasahiro Yamada u32 sr; /* Status Register RO */ 23*af930827SMasahiro Yamada u32 rhr; /* Receive Holding Register RO */ 24*af930827SMasahiro Yamada u32 thr; /* Transmit Holding Register WO */ 25*af930827SMasahiro Yamada u32 brgr; /* Baud Rate Generator Register RW */ 26*af930827SMasahiro Yamada u32 res1[7];/* 0x0024 - 0x003C Reserved */ 27*af930827SMasahiro Yamada u32 cidr; /* Chip ID Register RO */ 28*af930827SMasahiro Yamada u32 exid; /* Chip ID Extension Register RO */ 29*af930827SMasahiro Yamada u32 fnr; /* Force NTRST Register RW */ 30*af930827SMasahiro Yamada } at91_dbu_t; 31*af930827SMasahiro Yamada 32*af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 33*af930827SMasahiro Yamada 34*af930827SMasahiro Yamada #define AT91_DBU_CID_ARCH_MASK 0x0ff00000 35*af930827SMasahiro Yamada #define AT91_DBU_CID_ARCH_9xx 0x01900000 36*af930827SMasahiro Yamada #define AT91_DBU_CID_ARCH_9XExx 0x02900000 37*af930827SMasahiro Yamada 38*af930827SMasahiro Yamada #endif 39