1*62011840SMasahiro Yamada /* 2*62011840SMasahiro Yamada * (C) Copyright 2007-2008 3*62011840SMasahiro Yamada * Stelian Pop <stelian@popies.net> 4*62011840SMasahiro Yamada * Lead Tech Design <www.leadtechdesign.com> 5*62011840SMasahiro Yamada * 6*62011840SMasahiro Yamada * (C) Copyright 2013 7*62011840SMasahiro Yamada * Bo Shen <voice.shen@atmel.com> 8*62011840SMasahiro Yamada * 9*62011840SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 10*62011840SMasahiro Yamada */ 11*62011840SMasahiro Yamada 12*62011840SMasahiro Yamada #include <common.h> 13*62011840SMasahiro Yamada #include <asm/io.h> 14*62011840SMasahiro Yamada #include <asm/arch/hardware.h> 15*62011840SMasahiro Yamada #include <asm/arch/at91_pit.h> 16*62011840SMasahiro Yamada #include <asm/arch/clk.h> 17*62011840SMasahiro Yamada #include <div64.h> 18*62011840SMasahiro Yamada 19*62011840SMasahiro Yamada #if !defined(CONFIG_AT91FAMILY) 20*62011840SMasahiro Yamada # error You need to define CONFIG_AT91FAMILY in your board config! 21*62011840SMasahiro Yamada #endif 22*62011840SMasahiro Yamada 23*62011840SMasahiro Yamada DECLARE_GLOBAL_DATA_PTR; 24*62011840SMasahiro Yamada 25*62011840SMasahiro Yamada /* 26*62011840SMasahiro Yamada * We're using the SAMA5D3x PITC in 32 bit mode, by 27*62011840SMasahiro Yamada * setting the 20 bit counter period to its maximum (0xfffff). 28*62011840SMasahiro Yamada * (See the relevant data sheets to understand that this really works) 29*62011840SMasahiro Yamada * 30*62011840SMasahiro Yamada * We do also mimic the typical powerpc way of incrementing 31*62011840SMasahiro Yamada * two 32 bit registers called tbl and tbu. 32*62011840SMasahiro Yamada * 33*62011840SMasahiro Yamada * Those registers increment at 1/16 the main clock rate. 34*62011840SMasahiro Yamada */ 35*62011840SMasahiro Yamada 36*62011840SMasahiro Yamada #define TIMER_LOAD_VAL 0xfffff 37*62011840SMasahiro Yamada 38*62011840SMasahiro Yamada /* 39*62011840SMasahiro Yamada * Use the PITC in full 32 bit incrementing mode 40*62011840SMasahiro Yamada */ timer_init(void)41*62011840SMasahiro Yamadaint timer_init(void) 42*62011840SMasahiro Yamada { 43*62011840SMasahiro Yamada at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; 44*62011840SMasahiro Yamada 45*62011840SMasahiro Yamada /* Enable PITC Clock */ 46*62011840SMasahiro Yamada at91_periph_clk_enable(ATMEL_ID_PIT); 47*62011840SMasahiro Yamada 48*62011840SMasahiro Yamada /* Enable PITC */ 49*62011840SMasahiro Yamada writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); 50*62011840SMasahiro Yamada 51*62011840SMasahiro Yamada gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; 52*62011840SMasahiro Yamada 53*62011840SMasahiro Yamada return 0; 54*62011840SMasahiro Yamada } 55*62011840SMasahiro Yamada 56*62011840SMasahiro Yamada /* 57*62011840SMasahiro Yamada * Return the number of timer ticks per second. 58*62011840SMasahiro Yamada */ get_tbclk(void)59*62011840SMasahiro Yamadaulong get_tbclk(void) 60*62011840SMasahiro Yamada { 61*62011840SMasahiro Yamada return gd->arch.timer_rate_hz; 62*62011840SMasahiro Yamada } 63