141d41a93SBo Shen/* 241d41a93SBo Shen * Copyright (C) 2015 Atmel Corporation 341d41a93SBo Shen * Bo Shen <voice.shen@atmel.com> 441d41a93SBo Shen * 541d41a93SBo Shen * SPDX-License-Identifier: GPL-2.0+ 641d41a93SBo Shen */ 741d41a93SBo Shen 841d41a93SBo ShenMEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ 941d41a93SBo Shen LENGTH = CONFIG_SPL_MAX_SIZE } 1041d41a93SBo ShenMEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ 1141d41a93SBo Shen LENGTH = CONFIG_SPL_BSS_MAX_SIZE } 1241d41a93SBo Shen 1341d41a93SBo ShenOUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 1441d41a93SBo ShenOUTPUT_ARCH(arm) 1541d41a93SBo ShenENTRY(_start) 1641d41a93SBo ShenSECTIONS 1741d41a93SBo Shen{ 1841d41a93SBo Shen .text : 1941d41a93SBo Shen { 2041d41a93SBo Shen __start = .; 2141d41a93SBo Shen *(.vectors) 2241d41a93SBo Shen arch/arm/cpu/arm926ejs/start.o (.text*) 2341d41a93SBo Shen *(.text*) 2441d41a93SBo Shen } >.sram 2541d41a93SBo Shen 2641d41a93SBo Shen . = ALIGN(4); 2741d41a93SBo Shen .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram 2841d41a93SBo Shen 2941d41a93SBo Shen . = ALIGN(4); 3041d41a93SBo Shen .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram 3141d41a93SBo Shen 3241d41a93SBo Shen . = ALIGN(4); 33*f8a48263STom Rini .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram 34*f8a48263STom Rini 35*f8a48263STom Rini . = ALIGN(4); 3641d41a93SBo Shen __image_copy_end = .; 3741d41a93SBo Shen 3841d41a93SBo Shen .end : 3941d41a93SBo Shen { 4041d41a93SBo Shen *(.__end) 4141d41a93SBo Shen } >.sram 4241d41a93SBo Shen 4341d41a93SBo Shen .bss : 4441d41a93SBo Shen { 4541d41a93SBo Shen . = ALIGN(4); 4641d41a93SBo Shen __bss_start = .; 4741d41a93SBo Shen *(.bss*) 4841d41a93SBo Shen . = ALIGN(4); 4941d41a93SBo Shen __bss_end = .; 5041d41a93SBo Shen } >.sdram 5141d41a93SBo Shen} 52