1*62011840SMasahiro Yamada/* 2*62011840SMasahiro Yamada * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and 3*62011840SMasahiro Yamada * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) 4*62011840SMasahiro Yamada * 5*62011840SMasahiro Yamada * Modified for the at91rm9200dk board by 6*62011840SMasahiro Yamada * (C) Copyright 2004 7*62011840SMasahiro Yamada * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 8*62011840SMasahiro Yamada * 9*62011840SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 10*62011840SMasahiro Yamada */ 11*62011840SMasahiro Yamada 12*62011840SMasahiro Yamada#include <config.h> 13*62011840SMasahiro Yamada 14*62011840SMasahiro Yamada#ifndef CONFIG_SKIP_LOWLEVEL_INIT 15*62011840SMasahiro Yamada 16*62011840SMasahiro Yamada#include <asm/arch/hardware.h> 17*62011840SMasahiro Yamada#include <asm/arch/at91_mc.h> 18*62011840SMasahiro Yamada#include <asm/arch/at91_pmc.h> 19*62011840SMasahiro Yamada#include <asm/arch/at91_pio.h> 20*62011840SMasahiro Yamada 21*62011840SMasahiro Yamada#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */ 22*62011840SMasahiro Yamada 23*62011840SMasahiro Yamada_MTEXT_BASE: 24*62011840SMasahiro Yamada#undef START_FROM_MEM 25*62011840SMasahiro Yamada#ifdef START_FROM_MEM 26*62011840SMasahiro Yamada .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1 27*62011840SMasahiro Yamada#else 28*62011840SMasahiro Yamada .word CONFIG_SYS_TEXT_BASE 29*62011840SMasahiro Yamada#endif 30*62011840SMasahiro Yamada 31*62011840SMasahiro Yamada.globl lowlevel_init 32*62011840SMasahiro Yamadalowlevel_init: 33*62011840SMasahiro Yamada ldr r1, =AT91_ASM_PMC_MOR 34*62011840SMasahiro Yamada /* Main oscillator Enable register */ 35*62011840SMasahiro Yamada#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR 36*62011840SMasahiro Yamada ldr r0, =0x0000FF01 /* Enable main oscillator */ 37*62011840SMasahiro Yamada#else 38*62011840SMasahiro Yamada ldr r0, =0x0000FF00 /* Disable main oscillator */ 39*62011840SMasahiro Yamada#endif 40*62011840SMasahiro Yamada str r0, [r1] /*AT91C_CKGR_MOR] */ 41*62011840SMasahiro Yamada /* Add loop to compensate Main Oscillator startup time */ 42*62011840SMasahiro Yamada ldr r0, =0x00000010 43*62011840SMasahiro YamadaLoopOsc: 44*62011840SMasahiro Yamada subs r0, r0, #1 45*62011840SMasahiro Yamada bhi LoopOsc 46*62011840SMasahiro Yamada 47*62011840SMasahiro Yamada /* memory control configuration */ 48*62011840SMasahiro Yamada /* this isn't very elegant, but what the heck */ 49*62011840SMasahiro Yamada ldr r0, =SMRDATA 50*62011840SMasahiro Yamada ldr r1, _MTEXT_BASE 51*62011840SMasahiro Yamada sub r0, r0, r1 52*62011840SMasahiro Yamada ldr r2, =SMRDATAE 53*62011840SMasahiro Yamada sub r2, r2, r1 54*62011840SMasahiro Yamadapllloop: 55*62011840SMasahiro Yamada /* the address */ 56*62011840SMasahiro Yamada ldr r1, [r0], #4 57*62011840SMasahiro Yamada /* the value */ 58*62011840SMasahiro Yamada ldr r3, [r0], #4 59*62011840SMasahiro Yamada str r3, [r1] 60*62011840SMasahiro Yamada cmp r2, r0 61*62011840SMasahiro Yamada bne pllloop 62*62011840SMasahiro Yamada /* delay - this is all done by guess */ 63*62011840SMasahiro Yamada ldr r0, =0x00010000 64*62011840SMasahiro Yamada /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */ 65*62011840SMasahiro Yamadalock: 66*62011840SMasahiro Yamada subs r0, r0, #1 67*62011840SMasahiro Yamada bhi lock 68*62011840SMasahiro Yamada ldr r0, =SMRDATA1 69*62011840SMasahiro Yamada ldr r1, _MTEXT_BASE 70*62011840SMasahiro Yamada sub r0, r0, r1 71*62011840SMasahiro Yamada ldr r2, =SMRDATA1E 72*62011840SMasahiro Yamada sub r2, r2, r1 73*62011840SMasahiro Yamadasdinit: 74*62011840SMasahiro Yamada /* the address */ 75*62011840SMasahiro Yamada ldr r1, [r0], #4 76*62011840SMasahiro Yamada /* the value */ 77*62011840SMasahiro Yamada ldr r3, [r0], #4 78*62011840SMasahiro Yamada str r3, [r1] 79*62011840SMasahiro Yamada cmp r2, r0 80*62011840SMasahiro Yamada bne sdinit 81*62011840SMasahiro Yamada 82*62011840SMasahiro Yamada /* switch from FastBus to Asynchronous clock mode */ 83*62011840SMasahiro Yamada mrc p15, 0, r0, c1, c0, 0 84*62011840SMasahiro Yamada orr r0, r0, #ARM920T_CONTROL 85*62011840SMasahiro Yamada mcr p15, 0, r0, c1, c0, 0 86*62011840SMasahiro Yamada 87*62011840SMasahiro Yamada /* everything is fine now */ 88*62011840SMasahiro Yamada mov pc, lr 89*62011840SMasahiro Yamada 90*62011840SMasahiro Yamada .ltorg 91*62011840SMasahiro Yamada 92*62011840SMasahiro YamadaSMRDATA: 93*62011840SMasahiro Yamada .word AT91_ASM_MC_EBI_CFG 94*62011840SMasahiro Yamada .word CONFIG_SYS_EBI_CFGR_VAL 95*62011840SMasahiro Yamada .word AT91_ASM_MC_SMC_CSR0 96*62011840SMasahiro Yamada .word CONFIG_SYS_SMC_CSR0_VAL 97*62011840SMasahiro Yamada .word AT91_ASM_PMC_PLLAR 98*62011840SMasahiro Yamada .word CONFIG_SYS_PLLAR_VAL 99*62011840SMasahiro Yamada .word AT91_ASM_PMC_PLLBR 100*62011840SMasahiro Yamada .word CONFIG_SYS_PLLBR_VAL 101*62011840SMasahiro Yamada .word AT91_ASM_PMC_MCKR 102*62011840SMasahiro Yamada .word CONFIG_SYS_MCKR_VAL 103*62011840SMasahiro YamadaSMRDATAE: 104*62011840SMasahiro Yamada /* here there's a delay */ 105*62011840SMasahiro YamadaSMRDATA1: 106*62011840SMasahiro Yamada .word AT91_ASM_PIOC_ASR 107*62011840SMasahiro Yamada .word CONFIG_SYS_PIOC_ASR_VAL 108*62011840SMasahiro Yamada .word AT91_ASM_PIOC_BSR 109*62011840SMasahiro Yamada .word CONFIG_SYS_PIOC_BSR_VAL 110*62011840SMasahiro Yamada .word AT91_ASM_PIOC_PDR 111*62011840SMasahiro Yamada .word CONFIG_SYS_PIOC_PDR_VAL 112*62011840SMasahiro Yamada .word AT91_ASM_MC_EBI_CSA 113*62011840SMasahiro Yamada .word CONFIG_SYS_EBI_CSA_VAL 114*62011840SMasahiro Yamada .word AT91_ASM_MC_SDRAMC_CR 115*62011840SMasahiro Yamada .word CONFIG_SYS_SDRC_CR_VAL 116*62011840SMasahiro Yamada .word AT91_ASM_MC_SDRAMC_MR 117*62011840SMasahiro Yamada .word CONFIG_SYS_SDRC_MR_VAL 118*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 119*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 120*62011840SMasahiro Yamada .word AT91_ASM_MC_SDRAMC_MR 121*62011840SMasahiro Yamada .word CONFIG_SYS_SDRC_MR_VAL1 122*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 123*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 124*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 125*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 126*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 127*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 128*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 129*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 130*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 131*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 132*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 133*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 134*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 135*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 136*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 137*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 138*62011840SMasahiro Yamada .word AT91_ASM_MC_SDRAMC_MR 139*62011840SMasahiro Yamada .word CONFIG_SYS_SDRC_MR_VAL2 140*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM1 141*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 142*62011840SMasahiro Yamada .word AT91_ASM_MC_SDRAMC_TR 143*62011840SMasahiro Yamada .word CONFIG_SYS_SDRC_TR_VAL 144*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 145*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 146*62011840SMasahiro Yamada .word AT91_ASM_MC_SDRAMC_MR 147*62011840SMasahiro Yamada .word CONFIG_SYS_SDRC_MR_VAL3 148*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM 149*62011840SMasahiro Yamada .word CONFIG_SYS_SDRAM_VAL 150*62011840SMasahiro YamadaSMRDATA1E: 151*62011840SMasahiro Yamada /* SMRDATA1 is 176 bytes long */ 152*62011840SMasahiro Yamada#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 153