1*f6a6a9f0Smaxims@google.com /* 2*f6a6a9f0Smaxims@google.com * Copyright (c) 2016 Google, Inc 3*f6a6a9f0Smaxims@google.com * 4*f6a6a9f0Smaxims@google.com * SPDX-License-Identifier: GPL-2.0+ 5*f6a6a9f0Smaxims@google.com */ 6*f6a6a9f0Smaxims@google.com #include <common.h> 7*f6a6a9f0Smaxims@google.com #include <dm.h> 8*f6a6a9f0Smaxims@google.com #include <ram.h> 9*f6a6a9f0Smaxims@google.com #include <timer.h> 10*f6a6a9f0Smaxims@google.com #include <asm/io.h> 11*f6a6a9f0Smaxims@google.com #include <asm/arch/timer.h> 12*f6a6a9f0Smaxims@google.com #include <asm/arch/wdt.h> 13*f6a6a9f0Smaxims@google.com #include <linux/err.h> 14*f6a6a9f0Smaxims@google.com #include <dm/uclass.h> 15*f6a6a9f0Smaxims@google.com 16*f6a6a9f0Smaxims@google.com /* 17*f6a6a9f0Smaxims@google.com * Second Watchdog Timer by default is configured 18*f6a6a9f0Smaxims@google.com * to trigger secondary boot source. 19*f6a6a9f0Smaxims@google.com */ 20*f6a6a9f0Smaxims@google.com #define AST_2ND_BOOT_WDT 1 21*f6a6a9f0Smaxims@google.com 22*f6a6a9f0Smaxims@google.com /* 23*f6a6a9f0Smaxims@google.com * Third Watchdog Timer by default is configured 24*f6a6a9f0Smaxims@google.com * to toggle Flash address mode switch before reset. 25*f6a6a9f0Smaxims@google.com */ 26*f6a6a9f0Smaxims@google.com #define AST_FLASH_ADDR_DETECT_WDT 2 27*f6a6a9f0Smaxims@google.com 28*f6a6a9f0Smaxims@google.com DECLARE_GLOBAL_DATA_PTR; 29*f6a6a9f0Smaxims@google.com lowlevel_init(void)30*f6a6a9f0Smaxims@google.comvoid lowlevel_init(void) 31*f6a6a9f0Smaxims@google.com { 32*f6a6a9f0Smaxims@google.com /* 33*f6a6a9f0Smaxims@google.com * These two watchdogs need to be stopped as soon as possible, 34*f6a6a9f0Smaxims@google.com * otherwise the board might hang. By default they are set to 35*f6a6a9f0Smaxims@google.com * a very short timeout and even simple debug write to serial 36*f6a6a9f0Smaxims@google.com * console early in the init process might cause them to fire. 37*f6a6a9f0Smaxims@google.com */ 38*f6a6a9f0Smaxims@google.com struct ast_wdt *flash_addr_wdt = 39*f6a6a9f0Smaxims@google.com (struct ast_wdt *)(WDT_BASE + 40*f6a6a9f0Smaxims@google.com sizeof(struct ast_wdt) * 41*f6a6a9f0Smaxims@google.com AST_FLASH_ADDR_DETECT_WDT); 42*f6a6a9f0Smaxims@google.com 43*f6a6a9f0Smaxims@google.com clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN); 44*f6a6a9f0Smaxims@google.com 45*f6a6a9f0Smaxims@google.com #ifndef CONFIG_FIRMWARE_2ND_BOOT 46*f6a6a9f0Smaxims@google.com struct ast_wdt *sec_boot_wdt = 47*f6a6a9f0Smaxims@google.com (struct ast_wdt *)(WDT_BASE + 48*f6a6a9f0Smaxims@google.com sizeof(struct ast_wdt) * 49*f6a6a9f0Smaxims@google.com AST_2ND_BOOT_WDT); 50*f6a6a9f0Smaxims@google.com 51*f6a6a9f0Smaxims@google.com clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN); 52*f6a6a9f0Smaxims@google.com #endif 53*f6a6a9f0Smaxims@google.com } 54*f6a6a9f0Smaxims@google.com board_init(void)55*f6a6a9f0Smaxims@google.comint board_init(void) 56*f6a6a9f0Smaxims@google.com { 57*f6a6a9f0Smaxims@google.com gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 58*f6a6a9f0Smaxims@google.com 59*f6a6a9f0Smaxims@google.com return 0; 60*f6a6a9f0Smaxims@google.com } 61*f6a6a9f0Smaxims@google.com dram_init(void)62*f6a6a9f0Smaxims@google.comint dram_init(void) 63*f6a6a9f0Smaxims@google.com { 64*f6a6a9f0Smaxims@google.com struct udevice *dev; 65*f6a6a9f0Smaxims@google.com struct ram_info ram; 66*f6a6a9f0Smaxims@google.com int ret; 67*f6a6a9f0Smaxims@google.com 68*f6a6a9f0Smaxims@google.com ret = uclass_get_device(UCLASS_RAM, 0, &dev); 69*f6a6a9f0Smaxims@google.com if (ret) { 70*f6a6a9f0Smaxims@google.com debug("DRAM FAIL1\r\n"); 71*f6a6a9f0Smaxims@google.com return ret; 72*f6a6a9f0Smaxims@google.com } 73*f6a6a9f0Smaxims@google.com 74*f6a6a9f0Smaxims@google.com ret = ram_get_info(dev, &ram); 75*f6a6a9f0Smaxims@google.com if (ret) { 76*f6a6a9f0Smaxims@google.com debug("DRAM FAIL2\r\n"); 77*f6a6a9f0Smaxims@google.com return ret; 78*f6a6a9f0Smaxims@google.com } 79*f6a6a9f0Smaxims@google.com 80*f6a6a9f0Smaxims@google.com gd->ram_size = ram.size; 81*f6a6a9f0Smaxims@google.com 82*f6a6a9f0Smaxims@google.com return 0; 83*f6a6a9f0Smaxims@google.com } 84