1 /* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <linux/compiler.h> 10 #include <efi_loader.h> 11 #include <iomem.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IRQ) 15 16 int interrupt_init(void) 17 { 18 return 0; 19 } 20 21 void enable_interrupts(void) 22 { 23 return; 24 } 25 26 int disable_interrupts(void) 27 { 28 return 0; 29 } 30 #endif 31 32 #if (!defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)) 33 #define REG_BITS(val, shift, mask) (((val) >> (shift)) & (mask)) 34 35 void show_regs(struct pt_regs *regs) 36 { 37 int i; 38 int el = current_el(); 39 const char *h_scr_name[] = { 40 [2] = "HCR_EL2", 41 [3] = "SCR_EL3", 42 }; 43 const char *esr_bits_ec[] = { 44 [0] = "EC[31:26] == 000000, Exception with an unknown reason", 45 [1] = "EC[31:26] == 000001, Exception from a WFI or WFE instruction", 46 [3] = "EC[31:26] == 000011, Exception from an MCR or MRC access", 47 [4] = "EC[31:26] == 000100, Exception from an MCRR or MRRC access", 48 [5] = "EC[31:26] == 000101, Exception from an MCR or MRC access", 49 [6] = "EC[31:26] == 000110, Exception from an LDC or STC access to CP14", 50 [7] = "EC[31:26] == 000111, Exception from an access to an Advanced SIMD or floating-point register, resulting from CPACR_EL1.FPEN or CPTR_ELx.TFP", 51 [8] = "EC[31:26] == 001000, Exception from an MCR or MRC access", 52 [12] = "EC[31:26] == 001100, Exception from an MCRR or MRRC access", 53 [14] = "EC[31:26] == 001110, Exception from an Illegal execution state, or a PC or SP alignment fault", 54 [10] = "EC[31:26] == 010001, Exception from HVC or SVC instruction execution", 55 [18] = "EC[31:26] == 010010, Exception from HVC or SVC instruction execution", 56 [19] = "EC[31:26] == 010011, Exception from SMC instruction execution in AArch32 state", 57 [21] = "EC[31:26] == 010101, Exception from HVC or SVC instruction execution", 58 [22] = "EC[31:26] == 010110, Exception from HVC or SVC instruction execution", 59 [23] = "EC[31:26] == 010111, Exception from SMC instruction execution in AArch64 state", 60 [24] = "EC[31:26] == 011000, Exception from MSR, MRS, or System instruction execution in AArch64 state", 61 [31] = "EC[31:26] == 011111, IMPLEMENTATION DEFINED exception to EL3", 62 [32] = "EC[31:26] == 100000, Exception from an Instruction abort", 63 [33] = "EC[31:26] == 100001, Exception from an Instruction abort", 64 [34] = "EC[31:26] == 100010, Exception from an Illegal execution state, or a PC or SP alignment fault", 65 [36] = "EC[31:26] == 100100, Exception from a Data abort, from lower exception level", 66 [37] = "EC[31:26] == 100101, Exception from a Data abort, from current exception level", 67 [38] = "EC[31:26] == 100110, Exception from an Illegal execution state, or a PC or SP alignment fault", 68 [40] = "EC[31:26] == 101000, Exception from a trapped Floating-point exception", 69 [44] = "EC[31:26] == 101100, Exception from a trapped Floating-point exception", 70 [47] = "EC[31:26] == 101111, SError interrupt", 71 [48] = "EC[31:26] == 110000, Exception from a Breakpoint or Vector Catch debug event", 72 [49] = "EC[31:26] == 110001, Exception from a Breakpoint or Vector Catch debug event", 73 [50] = "EC[31:26] == 110010, Exception from a Software Step debug event", 74 [51] = "EC[31:26] == 110011, Exception from a Software Step debug event", 75 [52] = "EC[31:26] == 110100, Exception from a Watchpoint debug event", 76 [53] = "EC[31:26] == 110101, Exception from a Watchpoint debug event", 77 [56] = "EC[31:26] == 111000, Exception from execution of a Software Breakpoint instructio", 78 }; 79 const char *esr_bits_il[] = { 80 "IL[25] == 0, 16-bit instruction trapped", 81 "IL[25] == 1, 32-bit instruction trapped", 82 }; 83 const char *daif_bits_f[] = { 84 "F[6] == 0, FIQ not masked", 85 "F[6] == 1, FIQ masked", 86 }; 87 const char *daif_bits_i[] = { 88 "I[7] == 0, IRQ not masked", 89 "I[7] == 1, IRQ masked", 90 }; 91 const char *daif_bits_a[] = { 92 "A[8] == 0, ABORT not masked", 93 "A[8] == 1, ABORT masked", 94 }; 95 const char *daif_bits_d[] = { 96 "D[9] == 0, DBG not masked", 97 "D[9] == 1, DBG masked", 98 }; 99 const char *spsr_bits_m_aarch32[] = { 100 [0] = "M[3:0] == 0000, User", 101 [1] = "M[3:0] == 0001, FIQ", 102 [2] = "M[3:0] == 0010, IRQ", 103 [3] = "M[3:0] == 0011, Supervisor", 104 [6] = "M[3:0] == 0110, Monitor", 105 [7] = "M[3:0] == 0111, Abort", 106 [10] = "M[3:0] == 1010, Hyp", 107 [11] = "M[3:0] == 1011, Undefined", 108 [15] = "M[3:0] == 1111, System", 109 }; 110 const char *spsr_bits_m_aarch64[] = { 111 [0] = "M[3:0] == 0000, EL0t", 112 [4] = "M[3:0] == 0100, EL1t", 113 [5] = "M[3:0] == 0101, EL1h", 114 [8] = "M[3:0] == 1000, EL2t", 115 [9] = "M[3:0] == 1001, EL2h", 116 [10] = "M[3:0] == 1100, EL3t", 117 [11] = "M[3:0] == 1101, EL3h", 118 }; 119 const char *spsr_bits_m[] = { 120 "M[4] == 0, Exception taken from AArch64", 121 "M[4] == 1, Exception taken from AArch32", 122 }; 123 const char *spsr_bits_f[] = { 124 "F[6] == 0, FIQ not masked", 125 "F[6] == 1, FIQ masked", 126 }; 127 const char *spsr_bits_i[] = { 128 "I[7] == 0, IRQ not masked", 129 "I[7] == 1, IRQ masked", 130 }; 131 const char *spsr_bits_a[] = { 132 "A[8] == 0, ABORT not masked", 133 "A[8] == 1, ABORT masked", 134 }; 135 const char *spsr_bits_d[] = { 136 "D[9] == 0, DBG not masked", 137 "D[9] == 1, DBG masked", 138 }; 139 const char *sctlr_bits_i[] = { 140 "I[12] == 0, Icache disabled", 141 "I[12] == 1, Icaches enabled", 142 }; 143 const char *sctlr_bits_c[] = { 144 "C[2] == 0, Dcache disabled", 145 "C[2] == 1, Dcache enabled", 146 }; 147 const char *sctlr_bits_m[] = { 148 "M[0] == 0, MMU disabled", 149 "M[0] == 1, MMU enabled", 150 }; 151 152 printf("* Relocate offset = %016lx\n", gd->reloc_off); 153 154 if (gd->flags & GD_FLG_RELOC) { 155 printf("* ELR(PC) = %016lx\n", regs->elr - gd->reloc_off); 156 printf("* LR = %016lx\n", regs->regs[30] - gd->reloc_off); 157 } else { 158 printf("* ELR(PC) = %016lx\n", regs->elr); 159 printf("* LR = %016lx\n", regs->regs[30]); 160 } 161 162 printf("* SP = %016lx\n", regs->sp); 163 printf("\n"); 164 165 /* 166 * System registers 167 */ 168 /* ESR_EL2 */ 169 printf("* ESR_EL%d = %016lx\n", el, regs->esr); 170 printf("\t%s\n", esr_bits_ec[REG_BITS(regs->esr, 26, 0x3f)]); 171 printf("\t%s\n", esr_bits_il[REG_BITS(regs->esr, 25, 0x01)]); 172 printf("\n"); 173 /* DAIF */ 174 printf("* DAIF = %016lx\n", regs->daif); 175 printf("\t%s\n", daif_bits_d[REG_BITS(regs->daif, 9, 0x1)]); 176 printf("\t%s\n", daif_bits_a[REG_BITS(regs->daif, 8, 0x1)]); 177 printf("\t%s\n", daif_bits_i[REG_BITS(regs->daif, 7, 0x1)]); 178 printf("\t%s\n", daif_bits_f[REG_BITS(regs->daif, 6, 0x1)]); 179 printf("\n"); 180 /* SPSR_ELx */ 181 printf("* SPSR_EL%d = %016lx\n", el, regs->spsr); 182 printf("\t%s\n", spsr_bits_d[REG_BITS(regs->spsr, 9, 0x1)]); 183 printf("\t%s\n", spsr_bits_a[REG_BITS(regs->spsr, 8, 0x1)]); 184 printf("\t%s\n", spsr_bits_i[REG_BITS(regs->spsr, 7, 0x1)]); 185 printf("\t%s\n", spsr_bits_f[REG_BITS(regs->spsr, 6, 0x1)]); 186 printf("\t%s\n", spsr_bits_m[REG_BITS(regs->spsr, 4, 0x1)]); 187 if (REG_BITS(regs->spsr, 4, 0x1)) 188 printf("\t%s\n", spsr_bits_m_aarch32[REG_BITS(regs->spsr, 0, 0xf)]); 189 else 190 printf("\t%s\n", spsr_bits_m_aarch64[REG_BITS(regs->spsr, 0, 0xf)]); 191 printf("\n"); 192 /* SCTLR_EL2 */ 193 printf("* SCTLR_EL%d = %016lx\n", el, regs->sctlr); 194 printf("\t%s\n", sctlr_bits_i[REG_BITS(regs->sctlr, 12, 0x1)]); 195 printf("\t%s\n", sctlr_bits_c[REG_BITS(regs->sctlr, 2, 0x1)]); 196 printf("\t%s\n", sctlr_bits_m[REG_BITS(regs->sctlr, 0, 0x1)]); 197 printf("\n"); 198 199 /* Other */ 200 if (el >= 2) 201 printf("* %s = %016lx\n", h_scr_name[el], regs->hcr); 202 printf("* VBAR_EL%d = %016lx\n", el, regs->vbar); 203 printf("* TTBR0_EL%d = %016lx\n", el, regs->ttbr0); 204 printf("\n"); 205 206 for (i = 0; i < 29; i += 2) 207 printf("x%-2d: %016lx x%-2d: %016lx\n", 208 i, regs->regs[i], i+1, regs->regs[i+1]); 209 210 printf("\n"); 211 iomem_show("SP", regs->sp, 0x00, 0xfc); 212 213 printf("\n"); 214 215 #ifdef CONFIG_ROCKCHIP_CRASH_DUMP 216 iomem_show_by_compatible("-cru", 0, 0x400); 217 iomem_show_by_compatible("-pmucru", 0, 0x400); 218 iomem_show_by_compatible("-grf", 0, 0x400); 219 iomem_show_by_compatible("-pmugrf", 0, 0x400); 220 /* tobe add here ... */ 221 #endif 222 } 223 224 #else 225 void show_regs(struct pt_regs *regs) 226 { 227 int i; 228 229 if (gd->flags & GD_FLG_RELOC) { 230 printf("ELR: %lx\n", regs->elr - gd->reloc_off); 231 printf("LR: %lx\n", regs->regs[30] - gd->reloc_off); 232 } else { 233 printf("ELR: %lx\n", regs->elr); 234 printf("LR: %lx\n", regs->regs[30]); 235 } 236 for (i = 0; i < 29; i += 2) 237 printf("x%-2d: %016lx x%-2d: %016lx\n", 238 i, regs->regs[i], i+1, regs->regs[i+1]); 239 printf("\n"); 240 } 241 #endif 242 243 /* 244 * do_bad_sync handles the impossible case in the Synchronous Abort vector. 245 */ 246 void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr) 247 { 248 efi_restore_gd(); 249 printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr); 250 show_regs(pt_regs); 251 panic("Resetting CPU ...\n"); 252 } 253 254 /* 255 * do_bad_irq handles the impossible case in the Irq vector. 256 */ 257 void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr) 258 { 259 efi_restore_gd(); 260 printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr); 261 show_regs(pt_regs); 262 panic("Resetting CPU ...\n"); 263 } 264 265 /* 266 * do_bad_fiq handles the impossible case in the Fiq vector. 267 */ 268 void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr) 269 { 270 efi_restore_gd(); 271 printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr); 272 show_regs(pt_regs); 273 panic("Resetting CPU ...\n"); 274 } 275 276 /* 277 * do_bad_error handles the impossible case in the Error vector. 278 */ 279 void do_bad_error(struct pt_regs *pt_regs, unsigned int esr) 280 { 281 efi_restore_gd(); 282 printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr); 283 show_regs(pt_regs); 284 panic("Resetting CPU ...\n"); 285 } 286 287 /* 288 * do_sync handles the Synchronous Abort exception. 289 */ 290 void do_sync(struct pt_regs *pt_regs, unsigned int esr) 291 { 292 efi_restore_gd(); 293 printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr); 294 show_regs(pt_regs); 295 panic("Resetting CPU ...\n"); 296 } 297 298 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IRQ) 299 /* 300 * do_irq handles the Irq exception. 301 */ 302 void do_irq(struct pt_regs *pt_regs, unsigned int esr) 303 { 304 efi_restore_gd(); 305 printf("\"Irq\" handler, esr 0x%08x\n", esr); 306 show_regs(pt_regs); 307 panic("Resetting CPU ...\n"); 308 } 309 #endif 310 311 /* 312 * do_fiq handles the Fiq exception. 313 */ 314 void do_fiq(struct pt_regs *pt_regs, unsigned int esr) 315 { 316 efi_restore_gd(); 317 printf("\"Fiq\" handler, esr 0x%08x\n", esr); 318 show_regs(pt_regs); 319 panic("Resetting CPU ...\n"); 320 } 321 322 /* 323 * do_error handles the Error exception. 324 * Errors are more likely to be processor specific, 325 * it is defined with weak attribute and can be redefined 326 * in processor specific code. 327 */ 328 void __weak do_error(struct pt_regs *pt_regs, unsigned int esr) 329 { 330 efi_restore_gd(); 331 printf("\"Error\" handler, esr 0x%08x\n", esr); 332 show_regs(pt_regs); 333 panic("Resetting CPU ...\n"); 334 } 335