1ea0364f1SPeter Tyser /* 2ea0364f1SPeter Tyser * (C) Copyright 2002 3ea0364f1SPeter Tyser * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4ea0364f1SPeter Tyser * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6ea0364f1SPeter Tyser */ 7ea0364f1SPeter Tyser 8ea0364f1SPeter Tyser /* for now: just dummy functions to satisfy the linker */ 9ea0364f1SPeter Tyser 10ea0364f1SPeter Tyser #include <common.h> 11*1dfdd9baSThierry Reding #include <malloc.h> 12ea0364f1SPeter Tyser 13fcfddfd5SJeroen Hofstee __weak void flush_cache(unsigned long start, unsigned long size) 14ea0364f1SPeter Tyser { 153fd968e9SMasahiro Yamada #if defined(CONFIG_CPU_ARM1136) 16ea0364f1SPeter Tyser 17b4ee1491SAlbert ARIBAUD #if !defined(CONFIG_SYS_ICACHE_OFF) 18b4ee1491SAlbert ARIBAUD asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ 19ea0364f1SPeter Tyser #endif 20b4ee1491SAlbert ARIBAUD 21b4ee1491SAlbert ARIBAUD #if !defined(CONFIG_SYS_DCACHE_OFF) 22b4ee1491SAlbert ARIBAUD asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ 23b4ee1491SAlbert ARIBAUD #endif 24b4ee1491SAlbert ARIBAUD 253fd968e9SMasahiro Yamada #endif /* CONFIG_CPU_ARM1136 */ 26b4ee1491SAlbert ARIBAUD 275d7b131dSMasahiro Yamada #ifdef CONFIG_CPU_ARM926EJS 28c3330e9dSHeiko Schocher /* test and clean, page 2-23 of arm926ejs manual */ 29c3330e9dSHeiko Schocher asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); 30c3330e9dSHeiko Schocher /* disable write buffer as well (page 2-22) */ 31c3330e9dSHeiko Schocher asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); 325d7b131dSMasahiro Yamada #endif /* CONFIG_CPU_ARM926EJS */ 33ea0364f1SPeter Tyser return; 34ea0364f1SPeter Tyser } 35e05f0079SAneesh V 36e05f0079SAneesh V /* 37e05f0079SAneesh V * Default implementation: 38e05f0079SAneesh V * do a range flush for the entire range 39e05f0079SAneesh V */ 40fcfddfd5SJeroen Hofstee __weak void flush_dcache_all(void) 41e05f0079SAneesh V { 42e05f0079SAneesh V flush_cache(0, ~0); 43e05f0079SAneesh V } 44cba4b180SAneesh V 45cba4b180SAneesh V /* 46cba4b180SAneesh V * Default implementation of enable_caches() 47cba4b180SAneesh V * Real implementation should be in platform code 48cba4b180SAneesh V */ 49fcfddfd5SJeroen Hofstee __weak void enable_caches(void) 50cba4b180SAneesh V { 51cba4b180SAneesh V puts("WARNING: Caches not enabled\n"); 52cba4b180SAneesh V } 53*1dfdd9baSThierry Reding 54*1dfdd9baSThierry Reding #ifdef CONFIG_SYS_NONCACHED_MEMORY 55*1dfdd9baSThierry Reding /* 56*1dfdd9baSThierry Reding * Reserve one MMU section worth of address space below the malloc() area that 57*1dfdd9baSThierry Reding * will be mapped uncached. 58*1dfdd9baSThierry Reding */ 59*1dfdd9baSThierry Reding static unsigned long noncached_start; 60*1dfdd9baSThierry Reding static unsigned long noncached_end; 61*1dfdd9baSThierry Reding static unsigned long noncached_next; 62*1dfdd9baSThierry Reding 63*1dfdd9baSThierry Reding void noncached_init(void) 64*1dfdd9baSThierry Reding { 65*1dfdd9baSThierry Reding phys_addr_t start, end; 66*1dfdd9baSThierry Reding size_t size; 67*1dfdd9baSThierry Reding 68*1dfdd9baSThierry Reding end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; 69*1dfdd9baSThierry Reding size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); 70*1dfdd9baSThierry Reding start = end - size; 71*1dfdd9baSThierry Reding 72*1dfdd9baSThierry Reding debug("mapping memory %pa-%pa non-cached\n", &start, &end); 73*1dfdd9baSThierry Reding 74*1dfdd9baSThierry Reding noncached_start = start; 75*1dfdd9baSThierry Reding noncached_end = end; 76*1dfdd9baSThierry Reding noncached_next = start; 77*1dfdd9baSThierry Reding 78*1dfdd9baSThierry Reding #ifndef CONFIG_SYS_DCACHE_OFF 79*1dfdd9baSThierry Reding mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); 80*1dfdd9baSThierry Reding #endif 81*1dfdd9baSThierry Reding } 82*1dfdd9baSThierry Reding 83*1dfdd9baSThierry Reding phys_addr_t noncached_alloc(size_t size, size_t align) 84*1dfdd9baSThierry Reding { 85*1dfdd9baSThierry Reding phys_addr_t next = ALIGN(noncached_next, align); 86*1dfdd9baSThierry Reding 87*1dfdd9baSThierry Reding if (next >= noncached_end || (noncached_end - next) < size) 88*1dfdd9baSThierry Reding return 0; 89*1dfdd9baSThierry Reding 90*1dfdd9baSThierry Reding debug("allocated %zu bytes of uncached memory @%pa\n", size, &next); 91*1dfdd9baSThierry Reding noncached_next = next + size; 92*1dfdd9baSThierry Reding 93*1dfdd9baSThierry Reding return next; 94*1dfdd9baSThierry Reding } 95*1dfdd9baSThierry Reding #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 96