xref: /rk3399_rockchip-uboot/arch/arm/lib/cache.c (revision 1a4596601fd395f3afb8f82f3f840c5e00bdd57a)
1ea0364f1SPeter Tyser /*
2ea0364f1SPeter Tyser  * (C) Copyright 2002
3ea0364f1SPeter Tyser  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4ea0364f1SPeter Tyser  *
5*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
6ea0364f1SPeter Tyser  */
7ea0364f1SPeter Tyser 
8ea0364f1SPeter Tyser /* for now: just dummy functions to satisfy the linker */
9ea0364f1SPeter Tyser 
10ea0364f1SPeter Tyser #include <common.h>
11ea0364f1SPeter Tyser 
124c93da7cSAneesh V void  __flush_cache(unsigned long start, unsigned long size)
13ea0364f1SPeter Tyser {
147f5eef93STom Rini #if defined(CONFIG_ARM1136)
15ea0364f1SPeter Tyser 	void arm1136_cache_flush(void);
16ea0364f1SPeter Tyser 
17ea0364f1SPeter Tyser 	arm1136_cache_flush();
18ea0364f1SPeter Tyser #endif
19c3330e9dSHeiko Schocher #ifdef CONFIG_ARM926EJS
20c3330e9dSHeiko Schocher 	/* test and clean, page 2-23 of arm926ejs manual */
21c3330e9dSHeiko Schocher 	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
22c3330e9dSHeiko Schocher 	/* disable write buffer as well (page 2-22) */
23c3330e9dSHeiko Schocher 	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
24c3330e9dSHeiko Schocher #endif
25ea0364f1SPeter Tyser 	return;
26ea0364f1SPeter Tyser }
274c93da7cSAneesh V void  flush_cache(unsigned long start, unsigned long size)
284c93da7cSAneesh V 	__attribute__((weak, alias("__flush_cache")));
29e05f0079SAneesh V 
30e05f0079SAneesh V /*
31e05f0079SAneesh V  * Default implementation:
32e05f0079SAneesh V  * do a range flush for the entire range
33e05f0079SAneesh V  */
34e05f0079SAneesh V void	__flush_dcache_all(void)
35e05f0079SAneesh V {
36e05f0079SAneesh V 	flush_cache(0, ~0);
37e05f0079SAneesh V }
38e05f0079SAneesh V void	flush_dcache_all(void)
39e05f0079SAneesh V 	__attribute__((weak, alias("__flush_dcache_all")));
40cba4b180SAneesh V 
41cba4b180SAneesh V 
42cba4b180SAneesh V /*
43cba4b180SAneesh V  * Default implementation of enable_caches()
44cba4b180SAneesh V  * Real implementation should be in platform code
45cba4b180SAneesh V  */
46cba4b180SAneesh V void __enable_caches(void)
47cba4b180SAneesh V {
48cba4b180SAneesh V 	puts("WARNING: Caches not enabled\n");
49cba4b180SAneesh V }
50cba4b180SAneesh V void enable_caches(void)
51cba4b180SAneesh V 	__attribute__((weak, alias("__enable_caches")));
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