1*1cfe9fa0SMasahiro Yamada/* 2*1cfe9fa0SMasahiro Yamada * arch/arm/include/debug/8250.S 3*1cfe9fa0SMasahiro Yamada * 4*1cfe9fa0SMasahiro Yamada * Copyright (C) 1994-2013 Russell King 5*1cfe9fa0SMasahiro Yamada * 6*1cfe9fa0SMasahiro Yamada * This program is free software; you can redistribute it and/or modify 7*1cfe9fa0SMasahiro Yamada * it under the terms of the GNU General Public License version 2 as 8*1cfe9fa0SMasahiro Yamada * published by the Free Software Foundation. 9*1cfe9fa0SMasahiro Yamada */ 10*1cfe9fa0SMasahiro Yamada#include <linux/serial_reg.h> 11*1cfe9fa0SMasahiro Yamada 12*1cfe9fa0SMasahiro Yamada .macro addruart, rp, rv, tmp 13*1cfe9fa0SMasahiro Yamada ldr \rp, =CONFIG_DEBUG_UART_PHYS 14*1cfe9fa0SMasahiro Yamada ldr \rv, =CONFIG_DEBUG_UART_VIRT 15*1cfe9fa0SMasahiro Yamada .endm 16*1cfe9fa0SMasahiro Yamada 17*1cfe9fa0SMasahiro Yamada#ifdef CONFIG_DEBUG_UART_8250_WORD 18*1cfe9fa0SMasahiro Yamada .macro store, rd, rx:vararg 19*1cfe9fa0SMasahiro Yamada str \rd, \rx 20*1cfe9fa0SMasahiro Yamada .endm 21*1cfe9fa0SMasahiro Yamada 22*1cfe9fa0SMasahiro Yamada .macro load, rd, rx:vararg 23*1cfe9fa0SMasahiro Yamada ldr \rd, \rx 24*1cfe9fa0SMasahiro Yamada .endm 25*1cfe9fa0SMasahiro Yamada#else 26*1cfe9fa0SMasahiro Yamada .macro store, rd, rx:vararg 27*1cfe9fa0SMasahiro Yamada strb \rd, \rx 28*1cfe9fa0SMasahiro Yamada .endm 29*1cfe9fa0SMasahiro Yamada 30*1cfe9fa0SMasahiro Yamada .macro load, rd, rx:vararg 31*1cfe9fa0SMasahiro Yamada ldrb \rd, \rx 32*1cfe9fa0SMasahiro Yamada .endm 33*1cfe9fa0SMasahiro Yamada#endif 34*1cfe9fa0SMasahiro Yamada 35*1cfe9fa0SMasahiro Yamada#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT 36*1cfe9fa0SMasahiro Yamada 37*1cfe9fa0SMasahiro Yamada .macro senduart,rd,rx 38*1cfe9fa0SMasahiro Yamada store \rd, [\rx, #UART_TX << UART_SHIFT] 39*1cfe9fa0SMasahiro Yamada .endm 40*1cfe9fa0SMasahiro Yamada 41*1cfe9fa0SMasahiro Yamada .macro busyuart,rd,rx 42*1cfe9fa0SMasahiro Yamada1002: load \rd, [\rx, #UART_LSR << UART_SHIFT] 43*1cfe9fa0SMasahiro Yamada and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE 44*1cfe9fa0SMasahiro Yamada teq \rd, #UART_LSR_TEMT | UART_LSR_THRE 45*1cfe9fa0SMasahiro Yamada bne 1002b 46*1cfe9fa0SMasahiro Yamada .endm 47*1cfe9fa0SMasahiro Yamada 48*1cfe9fa0SMasahiro Yamada .macro waituart,rd,rx 49*1cfe9fa0SMasahiro Yamada#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL 50*1cfe9fa0SMasahiro Yamada1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] 51*1cfe9fa0SMasahiro Yamada tst \rd, #UART_MSR_CTS 52*1cfe9fa0SMasahiro Yamada beq 1001b 53*1cfe9fa0SMasahiro Yamada#endif 54*1cfe9fa0SMasahiro Yamada .endm 55