11cfe9fa0SMasahiro Yamada/* 21cfe9fa0SMasahiro Yamada * arch/arm/include/debug/8250.S 31cfe9fa0SMasahiro Yamada * 41cfe9fa0SMasahiro Yamada * Copyright (C) 1994-2013 Russell King 51cfe9fa0SMasahiro Yamada * 6*93456512SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 71cfe9fa0SMasahiro Yamada */ 81cfe9fa0SMasahiro Yamada#include <linux/serial_reg.h> 91cfe9fa0SMasahiro Yamada 101cfe9fa0SMasahiro Yamada .macro addruart, rp, rv, tmp 111cfe9fa0SMasahiro Yamada ldr \rp, =CONFIG_DEBUG_UART_PHYS 121cfe9fa0SMasahiro Yamada ldr \rv, =CONFIG_DEBUG_UART_VIRT 131cfe9fa0SMasahiro Yamada .endm 141cfe9fa0SMasahiro Yamada 151cfe9fa0SMasahiro Yamada#ifdef CONFIG_DEBUG_UART_8250_WORD 161cfe9fa0SMasahiro Yamada .macro store, rd, rx:vararg 171cfe9fa0SMasahiro Yamada str \rd, \rx 181cfe9fa0SMasahiro Yamada .endm 191cfe9fa0SMasahiro Yamada 201cfe9fa0SMasahiro Yamada .macro load, rd, rx:vararg 211cfe9fa0SMasahiro Yamada ldr \rd, \rx 221cfe9fa0SMasahiro Yamada .endm 231cfe9fa0SMasahiro Yamada#else 241cfe9fa0SMasahiro Yamada .macro store, rd, rx:vararg 251cfe9fa0SMasahiro Yamada strb \rd, \rx 261cfe9fa0SMasahiro Yamada .endm 271cfe9fa0SMasahiro Yamada 281cfe9fa0SMasahiro Yamada .macro load, rd, rx:vararg 291cfe9fa0SMasahiro Yamada ldrb \rd, \rx 301cfe9fa0SMasahiro Yamada .endm 311cfe9fa0SMasahiro Yamada#endif 321cfe9fa0SMasahiro Yamada 331cfe9fa0SMasahiro Yamada#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT 341cfe9fa0SMasahiro Yamada 351cfe9fa0SMasahiro Yamada .macro senduart,rd,rx 361cfe9fa0SMasahiro Yamada store \rd, [\rx, #UART_TX << UART_SHIFT] 371cfe9fa0SMasahiro Yamada .endm 381cfe9fa0SMasahiro Yamada 391cfe9fa0SMasahiro Yamada .macro busyuart,rd,rx 401cfe9fa0SMasahiro Yamada1002: load \rd, [\rx, #UART_LSR << UART_SHIFT] 411cfe9fa0SMasahiro Yamada and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE 421cfe9fa0SMasahiro Yamada teq \rd, #UART_LSR_TEMT | UART_LSR_THRE 431cfe9fa0SMasahiro Yamada bne 1002b 441cfe9fa0SMasahiro Yamada .endm 451cfe9fa0SMasahiro Yamada 461cfe9fa0SMasahiro Yamada .macro waituart,rd,rx 471cfe9fa0SMasahiro Yamada#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL 481cfe9fa0SMasahiro Yamada1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] 491cfe9fa0SMasahiro Yamada tst \rd, #UART_MSR_CTS 501cfe9fa0SMasahiro Yamada beq 1001b 511cfe9fa0SMasahiro Yamada#endif 521cfe9fa0SMasahiro Yamada .endm 53