1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #ifdef CONFIG_ARM64 5 6 /* 7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 8 */ 9 #define CR_M (1 << 0) /* MMU enable */ 10 #define CR_A (1 << 1) /* Alignment abort enable */ 11 #define CR_C (1 << 2) /* Dcache enable */ 12 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 13 #define CR_I (1 << 12) /* Icache enable */ 14 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 15 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 16 17 #define PGTABLE_SIZE (0x10000) 18 /* 2MB granularity */ 19 #define MMU_SECTION_SHIFT 21 20 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) 21 22 #ifndef __ASSEMBLY__ 23 24 enum dcache_option { 25 DCACHE_OFF = 0x3, 26 }; 27 28 #define isb() \ 29 ({asm volatile( \ 30 "isb" : : : "memory"); \ 31 }) 32 33 #define wfi() \ 34 ({asm volatile( \ 35 "wfi" : : : "memory"); \ 36 }) 37 38 static inline unsigned int current_el(void) 39 { 40 unsigned int el; 41 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 42 return el >> 2; 43 } 44 45 static inline unsigned int get_sctlr(void) 46 { 47 unsigned int el, val; 48 49 el = current_el(); 50 if (el == 1) 51 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 52 else if (el == 2) 53 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 54 else 55 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 56 57 return val; 58 } 59 60 static inline void set_sctlr(unsigned int val) 61 { 62 unsigned int el; 63 64 el = current_el(); 65 if (el == 1) 66 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 67 else if (el == 2) 68 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 69 else 70 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 71 72 asm volatile("isb"); 73 } 74 75 static inline unsigned long read_mpidr(void) 76 { 77 unsigned long val; 78 79 asm volatile("mrs %0, mpidr_el1" : "=r" (val)); 80 81 return val; 82 } 83 84 #define BSP_COREID 0 85 86 void __asm_flush_dcache_all(void); 87 void __asm_invalidate_dcache_all(void); 88 void __asm_flush_dcache_range(u64 start, u64 end); 89 void __asm_invalidate_tlb_all(void); 90 void __asm_invalidate_icache_all(void); 91 int __asm_flush_l3_cache(void); 92 93 void armv8_switch_to_el2(void); 94 void armv8_switch_to_el1(void); 95 void gic_init(void); 96 void gic_send_sgi(unsigned long sgino); 97 void wait_for_wakeup(void); 98 void protect_secure_region(void); 99 void smp_kick_all_cpus(void); 100 101 void flush_l3_cache(void); 102 103 #endif /* __ASSEMBLY__ */ 104 105 #else /* CONFIG_ARM64 */ 106 107 #ifdef __KERNEL__ 108 109 #define CPU_ARCH_UNKNOWN 0 110 #define CPU_ARCH_ARMv3 1 111 #define CPU_ARCH_ARMv4 2 112 #define CPU_ARCH_ARMv4T 3 113 #define CPU_ARCH_ARMv5 4 114 #define CPU_ARCH_ARMv5T 5 115 #define CPU_ARCH_ARMv5TE 6 116 #define CPU_ARCH_ARMv5TEJ 7 117 #define CPU_ARCH_ARMv6 8 118 #define CPU_ARCH_ARMv7 9 119 120 /* 121 * CR1 bits (CP#15 CR1) 122 */ 123 #define CR_M (1 << 0) /* MMU enable */ 124 #define CR_A (1 << 1) /* Alignment abort enable */ 125 #define CR_C (1 << 2) /* Dcache enable */ 126 #define CR_W (1 << 3) /* Write buffer enable */ 127 #define CR_P (1 << 4) /* 32-bit exception handler */ 128 #define CR_D (1 << 5) /* 32-bit data address range */ 129 #define CR_L (1 << 6) /* Implementation defined */ 130 #define CR_B (1 << 7) /* Big endian */ 131 #define CR_S (1 << 8) /* System MMU protection */ 132 #define CR_R (1 << 9) /* ROM MMU protection */ 133 #define CR_F (1 << 10) /* Implementation defined */ 134 #define CR_Z (1 << 11) /* Implementation defined */ 135 #define CR_I (1 << 12) /* Icache enable */ 136 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 137 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 138 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 139 #define CR_DT (1 << 16) 140 #define CR_IT (1 << 18) 141 #define CR_ST (1 << 19) 142 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 143 #define CR_U (1 << 22) /* Unaligned access operation */ 144 #define CR_XP (1 << 23) /* Extended page tables */ 145 #define CR_VE (1 << 24) /* Vectored interrupts */ 146 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 147 #define CR_TRE (1 << 28) /* TEX remap enable */ 148 #define CR_AFE (1 << 29) /* Access flag enable */ 149 #define CR_TE (1 << 30) /* Thumb exception enable */ 150 151 #define PGTABLE_SIZE (4096 * 4) 152 153 /* 154 * This is used to ensure the compiler did actually allocate the register we 155 * asked it for some inline assembly sequences. Apparently we can't trust 156 * the compiler from one version to another so a bit of paranoia won't hurt. 157 * This string is meant to be concatenated with the inline asm string and 158 * will cause compilation to stop on mismatch. 159 * (for details, see gcc PR 15089) 160 */ 161 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 162 163 #ifndef __ASSEMBLY__ 164 165 /** 166 * save_boot_params() - Save boot parameters before starting reset sequence 167 * 168 * If you provide this function it will be called immediately U-Boot starts, 169 * both for SPL and U-Boot proper. 170 * 171 * All registers are unchanged from U-Boot entry. No registers need be 172 * preserved. 173 * 174 * This is not a normal C function. There is no stack. Return by branching to 175 * save_boot_params_ret. 176 * 177 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); 178 */ 179 180 /** 181 * save_boot_params_ret() - Return from save_boot_params() 182 * 183 * If you provide save_boot_params(), then you should jump back to this 184 * function when done. Try to preserve all registers. 185 * 186 * If your implementation of save_boot_params() is in C then it is acceptable 187 * to simply call save_boot_params_ret() at the end of your function. Since 188 * there is no link register set up, you cannot just exit the function. U-Boot 189 * will return to the (initialised) value of lr, and likely crash/hang. 190 * 191 * If your implementation of save_boot_params() is in assembler then you 192 * should use 'b' or 'bx' to return to save_boot_params_ret. 193 */ 194 void save_boot_params_ret(void); 195 196 #define isb() __asm__ __volatile__ ("" : : : "memory") 197 198 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 199 200 #ifdef __ARM_ARCH_7A__ 201 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 202 #else 203 #define wfi() 204 #endif 205 206 static inline unsigned int get_cr(void) 207 { 208 unsigned int val; 209 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 210 return val; 211 } 212 213 static inline void set_cr(unsigned int val) 214 { 215 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 216 : : "r" (val) : "cc"); 217 isb(); 218 } 219 220 static inline unsigned int get_dacr(void) 221 { 222 unsigned int val; 223 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 224 return val; 225 } 226 227 static inline void set_dacr(unsigned int val) 228 { 229 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 230 : : "r" (val) : "cc"); 231 isb(); 232 } 233 234 #ifdef CONFIG_ARMV7 235 /* Short-Descriptor Translation Table Level 1 Bits */ 236 #define TTB_SECT_NS_MASK (1 << 19) 237 #define TTB_SECT_NG_MASK (1 << 17) 238 #define TTB_SECT_S_MASK (1 << 16) 239 /* Note: TTB AP bits are set elsewhere */ 240 #define TTB_SECT_TEX(x) ((x & 0x7) << 12) 241 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) 242 #define TTB_SECT_XN_MASK (1 << 4) 243 #define TTB_SECT_C_MASK (1 << 3) 244 #define TTB_SECT_B_MASK (1 << 2) 245 #define TTB_SECT (2 << 0) 246 247 /* options available for data cache on each page */ 248 enum dcache_option { 249 DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | 250 TTB_SECT_XN_MASK | TTB_SECT, 251 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, 252 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, 253 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), 254 }; 255 #else 256 /* options available for data cache on each page */ 257 enum dcache_option { 258 DCACHE_OFF = 0x12, 259 DCACHE_WRITETHROUGH = 0x1a, 260 DCACHE_WRITEBACK = 0x1e, 261 DCACHE_WRITEALLOC = 0x16, 262 }; 263 #endif 264 265 /* Size of an MMU section */ 266 enum { 267 MMU_SECTION_SHIFT = 20, 268 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 269 }; 270 271 #ifdef CONFIG_ARMV7 272 /* TTBR0 bits */ 273 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 274 #define TTBR0_RGN_NC (0 << 3) 275 #define TTBR0_RGN_WBWA (1 << 3) 276 #define TTBR0_RGN_WT (2 << 3) 277 #define TTBR0_RGN_WB (3 << 3) 278 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ 279 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) 280 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) 281 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) 282 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) 283 #endif 284 285 /** 286 * Register an update to the page tables, and flush the TLB 287 * 288 * \param start start address of update in page table 289 * \param stop stop address of update in page table 290 */ 291 void mmu_page_table_flush(unsigned long start, unsigned long stop); 292 293 #endif /* __ASSEMBLY__ */ 294 295 #define arch_align_stack(x) (x) 296 297 #endif /* __KERNEL__ */ 298 299 #endif /* CONFIG_ARM64 */ 300 301 #ifndef __ASSEMBLY__ 302 /** 303 * Change the cache settings for a region. 304 * 305 * \param start start address of memory region to change 306 * \param size size of memory region to change 307 * \param option dcache option to select 308 */ 309 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 310 enum dcache_option option); 311 312 #ifdef CONFIG_SYS_NONCACHED_MEMORY 313 void noncached_init(void); 314 phys_addr_t noncached_alloc(size_t size, size_t align); 315 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 316 317 #endif /* __ASSEMBLY__ */ 318 319 #endif 320