1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #include <common.h> 5 #include <linux/compiler.h> 6 #include <asm/barriers.h> 7 8 #ifdef CONFIG_ARM64 9 10 /* 11 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 12 */ 13 #define CR_M (1 << 0) /* MMU enable */ 14 #define CR_A (1 << 1) /* Alignment abort enable */ 15 #define CR_C (1 << 2) /* Dcache enable */ 16 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 17 #define CR_I (1 << 12) /* Icache enable */ 18 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 19 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 20 21 #define ES_TO_AARCH64 1 22 #define ES_TO_AARCH32 0 23 24 /* 25 * SCR_EL3 bits definitions 26 */ 27 #define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */ 28 #define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */ 29 #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */ 30 #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */ 31 #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */ 32 #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */ 33 34 /* 35 * SPSR_EL3/SPSR_EL2 bits definitions 36 */ 37 #define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */ 38 #define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */ 39 #define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */ 40 #define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */ 41 #define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */ 42 #define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */ 43 #define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */ 44 #define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */ 45 #define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */ 46 #define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */ 47 #define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */ 48 #define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */ 49 #define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */ 50 51 /* 52 * CPTR_EL2 bits definitions 53 */ 54 #define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */ 55 56 /* 57 * SCTLR_EL2 bits definitions 58 */ 59 #define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\ 60 1 << 11 | 3 << 4) /* Reserved, RES1 */ 61 #define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */ 62 #define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */ 63 #define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */ 64 #define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */ 65 #define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */ 66 #define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */ 67 #define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */ 68 69 /* 70 * CNTHCTL_EL2 bits definitions 71 */ 72 #define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ 73 #define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ 74 75 /* 76 * HCR_EL2 bits definitions 77 */ 78 #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */ 79 #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ 80 #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ 81 #define HCR_EL2_TGE (1 << 27) /* Trap General Exceptions */ 82 #define HCR_EL2_AMO (1 << 5) /* Asynchronous External Abort and SError Interrupt routing */ 83 #define HCR_EL2_IMO (1 << 4) /* Physical IRQ Routing */ 84 #define HCR_EL2_FMO (1 << 3) /* Physical FIQ Routing */ 85 86 /* 87 * CPACR_EL1 bits definitions 88 */ 89 #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */ 90 91 /* 92 * SCTLR_EL1 bits definitions 93 */ 94 #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\ 95 1 << 11) /* Reserved, RES1 */ 96 #define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */ 97 #define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */ 98 #define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */ 99 #define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */ 100 #define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */ 101 #define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */ 102 #define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */ 103 #define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */ 104 #define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */ 105 #define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */ 106 #define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */ 107 #define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */ 108 #define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */ 109 #define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */ 110 #define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */ 111 #define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */ 112 #define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */ 113 114 #ifndef __ASSEMBLY__ 115 116 u64 get_page_table_size(void); 117 #define PGTABLE_SIZE get_page_table_size() 118 119 /* 2MB granularity */ 120 #define MMU_SECTION_SHIFT 21 121 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) 122 123 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */ 124 enum dcache_option { 125 DCACHE_OFF = 0 << 2, 126 DCACHE_WRITETHROUGH = 3 << 2, 127 DCACHE_WRITEBACK = 4 << 2, 128 DCACHE_WRITEALLOC = 4 << 2, 129 }; 130 131 #define wfi() \ 132 ({asm volatile( \ 133 "wfi" : : : "memory"); \ 134 }) 135 136 static inline unsigned int current_el(void) 137 { 138 unsigned int el; 139 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 140 return el >> 2; 141 } 142 143 static inline unsigned int get_sctlr(void) 144 { 145 unsigned int el, val; 146 147 el = current_el(); 148 if (el == 1) 149 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 150 else if (el == 2) 151 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 152 else 153 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 154 155 return val; 156 } 157 158 static inline void set_sctlr(unsigned int val) 159 { 160 unsigned int el; 161 162 el = current_el(); 163 if (el == 1) 164 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 165 else if (el == 2) 166 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 167 else 168 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 169 170 asm volatile("isb"); 171 } 172 173 static inline unsigned long read_mpidr(void) 174 { 175 unsigned long val; 176 177 asm volatile("mrs %0, mpidr_el1" : "=r" (val)); 178 179 return val; 180 } 181 182 static inline unsigned long get_daif(void) 183 { 184 unsigned long daif; 185 186 asm volatile("mrs %0, daif" : "=r" (daif)); 187 188 return daif; 189 } 190 191 static inline void disable_serror(void) 192 { 193 asm volatile("msr daifset, #0x04"); 194 } 195 196 #define BSP_COREID 0 197 198 void __asm_flush_dcache_all(void); 199 void __asm_invalidate_dcache_all(void); 200 void __asm_flush_dcache_range(u64 start, u64 end); 201 202 /** 203 * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses 204 * 205 * This performance an invalidate from @start to @end - 1. Both addresses 206 * should be cache-aligned, otherwise this function will align the start 207 * address and may continue past the end address. 208 * 209 * Data in the address range is evicted from the cache and is not written back 210 * to memory. 211 * 212 * @start: Start address to invalidate 213 * @end: End address to invalidate up to (exclusive) 214 */ 215 void __asm_invalidate_dcache_range(u64 start, u64 end); 216 void __asm_invalidate_tlb_all(void); 217 void __asm_invalidate_icache_all(void); 218 int __asm_invalidate_l3_dcache(void); 219 int __asm_flush_l3_dcache(void); 220 int __asm_invalidate_l3_icache(void); 221 void __asm_switch_ttbr(u64 new_ttbr); 222 223 /* 224 * Switch from EL3 to EL2 for ARMv8 225 * 226 * @args: For loading 64-bit OS, fdt address. 227 * For loading 32-bit OS, zero. 228 * @mach_nr: For loading 64-bit OS, zero. 229 * For loading 32-bit OS, machine nr 230 * @fdt_addr: For loading 64-bit OS, zero. 231 * For loading 32-bit OS, fdt address. 232 * @arg4: Input argument. 233 * @entry_point: kernel entry point 234 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 235 */ 236 void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, 237 u64 arg4, u64 entry_point, u64 es_flag); 238 /* 239 * Switch from EL2 to EL1 for ARMv8 240 * 241 * @args: For loading 64-bit OS, fdt address. 242 * For loading 32-bit OS, zero. 243 * @mach_nr: For loading 64-bit OS, zero. 244 * For loading 32-bit OS, machine nr 245 * @fdt_addr: For loading 64-bit OS, zero. 246 * For loading 32-bit OS, fdt address. 247 * @arg4: Input argument. 248 * @entry_point: kernel entry point 249 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 250 */ 251 void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr, 252 u64 arg4, u64 entry_point, u64 es_flag); 253 void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr, 254 u64 arg4, u64 entry_point); 255 void gic_init(void); 256 void gic_send_sgi(unsigned long sgino); 257 void wait_for_wakeup(void); 258 void protect_secure_region(void); 259 void smp_kick_all_cpus(void); 260 void smp_entry(u32 cpu); 261 262 void flush_l3_cache(void); 263 void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); 264 265 /* 266 *Issue a secure monitor call in accordance with ARM "SMC Calling convention", 267 * DEN0028A 268 * 269 * @args: input and output arguments 270 * 271 */ 272 void smc_call(struct pt_regs *args); 273 274 void __noreturn psci_system_reset(void); 275 void __noreturn psci_system_off(void); 276 277 #ifdef CONFIG_ARMV8_PSCI 278 extern char __secure_start[]; 279 extern char __secure_end[]; 280 extern char __secure_stack_start[]; 281 extern char __secure_stack_end[]; 282 283 void armv8_setup_psci(void); 284 void psci_setup_vectors(void); 285 void psci_arch_init(void); 286 #endif 287 288 #endif /* __ASSEMBLY__ */ 289 290 #else /* CONFIG_ARM64 */ 291 292 #ifdef __KERNEL__ 293 294 #define CPU_ARCH_UNKNOWN 0 295 #define CPU_ARCH_ARMv3 1 296 #define CPU_ARCH_ARMv4 2 297 #define CPU_ARCH_ARMv4T 3 298 #define CPU_ARCH_ARMv5 4 299 #define CPU_ARCH_ARMv5T 5 300 #define CPU_ARCH_ARMv5TE 6 301 #define CPU_ARCH_ARMv5TEJ 7 302 #define CPU_ARCH_ARMv6 8 303 #define CPU_ARCH_ARMv7 9 304 305 /* 306 * CR1 bits (CP#15 CR1) 307 */ 308 #define CR_M (1 << 0) /* MMU enable */ 309 #define CR_A (1 << 1) /* Alignment abort enable */ 310 #define CR_C (1 << 2) /* Dcache enable */ 311 #define CR_W (1 << 3) /* Write buffer enable */ 312 #define CR_P (1 << 4) /* 32-bit exception handler */ 313 #define CR_D (1 << 5) /* 32-bit data address range */ 314 #define CR_L (1 << 6) /* Implementation defined */ 315 #define CR_B (1 << 7) /* Big endian */ 316 #define CR_S (1 << 8) /* System MMU protection */ 317 #define CR_R (1 << 9) /* ROM MMU protection */ 318 #define CR_F (1 << 10) /* Implementation defined */ 319 #define CR_Z (1 << 11) /* Implementation defined */ 320 #define CR_I (1 << 12) /* Icache enable */ 321 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 322 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 323 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 324 #define CR_DT (1 << 16) 325 #define CR_IT (1 << 18) 326 #define CR_ST (1 << 19) 327 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 328 #define CR_U (1 << 22) /* Unaligned access operation */ 329 #define CR_XP (1 << 23) /* Extended page tables */ 330 #define CR_VE (1 << 24) /* Vectored interrupts */ 331 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 332 #define CR_TRE (1 << 28) /* TEX remap enable */ 333 #define CR_AFE (1 << 29) /* Access flag enable */ 334 #define CR_TE (1 << 30) /* Thumb exception enable */ 335 336 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE) 337 #define PGTABLE_SIZE (4096 * 5) 338 #elif !defined(PGTABLE_SIZE) 339 #define PGTABLE_SIZE (4096 * 4) 340 #endif 341 342 /* 343 * This is used to ensure the compiler did actually allocate the register we 344 * asked it for some inline assembly sequences. Apparently we can't trust 345 * the compiler from one version to another so a bit of paranoia won't hurt. 346 * This string is meant to be concatenated with the inline asm string and 347 * will cause compilation to stop on mismatch. 348 * (for details, see gcc PR 15089) 349 */ 350 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 351 352 #ifndef __ASSEMBLY__ 353 354 #ifdef CONFIG_ARMV7_LPAE 355 void switch_to_hypervisor_ret(void); 356 #endif 357 358 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 359 360 #ifdef __ARM_ARCH_7A__ 361 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 362 #else 363 #define wfi() 364 #endif 365 366 static inline unsigned long get_cpsr(void) 367 { 368 unsigned long cpsr; 369 370 asm volatile("mrs %0, cpsr" : "=r"(cpsr): ); 371 return cpsr; 372 } 373 374 static inline void set_cpsr(unsigned long cpsr) 375 { 376 asm volatile("msr cpsr_fsxc, %[cpsr]" : : [cpsr] "r" (cpsr)); 377 } 378 379 static inline void disable_async_abort(void) 380 { 381 unsigned long cpsr; 382 383 cpsr = get_cpsr(); 384 cpsr &= ~(1 << 8); 385 set_cpsr(cpsr); 386 } 387 388 static inline int is_hyp(void) 389 { 390 #ifdef CONFIG_ARMV7_LPAE 391 /* HYP mode requires LPAE ... */ 392 return ((get_cpsr() & 0x1f) == 0x1a); 393 #else 394 /* ... so without LPAE support we can optimize all hyp code away */ 395 return 0; 396 #endif 397 } 398 399 static inline unsigned int get_cr(void) 400 { 401 unsigned int val; 402 403 if (is_hyp()) 404 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val) 405 : 406 : "cc"); 407 else 408 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) 409 : 410 : "cc"); 411 return val; 412 } 413 414 static inline void set_cr(unsigned int val) 415 { 416 if (is_hyp()) 417 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" : 418 : "r" (val) 419 : "cc"); 420 else 421 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : 422 : "r" (val) 423 : "cc"); 424 isb(); 425 } 426 427 static inline unsigned int get_dacr(void) 428 { 429 unsigned int val; 430 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 431 return val; 432 } 433 434 static inline void set_dacr(unsigned int val) 435 { 436 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 437 : : "r" (val) : "cc"); 438 isb(); 439 } 440 441 static inline unsigned int read_mpidr(void) 442 { 443 unsigned int mpidr; 444 445 asm volatile ("mrc p15, 0, %[mpidr], c0, c0, 5" : [mpidr] "=r" (mpidr)); 446 return mpidr; 447 } 448 449 #ifdef CONFIG_ARMV7_LPAE 450 /* Long-Descriptor Translation Table Level 1/2 Bits */ 451 #define TTB_SECT_XN_MASK (1ULL << 54) 452 #define TTB_SECT_NG_MASK (1 << 11) 453 #define TTB_SECT_AF (1 << 10) 454 #define TTB_SECT_SH_MASK (3 << 8) 455 #define TTB_SECT_NS_MASK (1 << 5) 456 #define TTB_SECT_AP (1 << 6) 457 /* Note: TTB AP bits are set elsewhere */ 458 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */ 459 #define TTB_SECT (1 << 0) 460 #define TTB_PAGETABLE (3 << 0) 461 462 /* TTBCR flags */ 463 #define TTBCR_EAE (1 << 31) 464 #define TTBCR_T0SZ(x) ((x) << 0) 465 #define TTBCR_T1SZ(x) ((x) << 16) 466 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) 467 #define TTBCR_IRGN0_NC (0 << 8) 468 #define TTBCR_IRGN0_WBWA (1 << 8) 469 #define TTBCR_IRGN0_WT (2 << 8) 470 #define TTBCR_IRGN0_WBNWA (3 << 8) 471 #define TTBCR_IRGN0_MASK (3 << 8) 472 #define TTBCR_ORGN0_NC (0 << 10) 473 #define TTBCR_ORGN0_WBWA (1 << 10) 474 #define TTBCR_ORGN0_WT (2 << 10) 475 #define TTBCR_ORGN0_WBNWA (3 << 10) 476 #define TTBCR_ORGN0_MASK (3 << 10) 477 #define TTBCR_SHARED_NON (0 << 12) 478 #define TTBCR_SHARED_OUTER (2 << 12) 479 #define TTBCR_SHARED_INNER (3 << 12) 480 #define TTBCR_EPD0 (0 << 7) 481 482 /* 483 * Memory types 484 */ 485 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \ 486 (0xcc << (2 * 8)) | (0xff << (3 * 8))) 487 488 /* options available for data cache on each page */ 489 enum dcache_option { 490 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK, 491 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), 492 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), 493 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3), 494 }; 495 #elif defined(CONFIG_CPU_V7) 496 /* Short-Descriptor Translation Table Level 1 Bits */ 497 #define TTB_SECT_NS_MASK (1 << 19) 498 #define TTB_SECT_NG_MASK (1 << 17) 499 #define TTB_SECT_S_MASK (1 << 16) 500 /* Note: TTB AP bits are set elsewhere */ 501 #define TTB_SECT_AP (3 << 10) 502 #define TTB_SECT_TEX(x) ((x & 0x7) << 12) 503 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) 504 #define TTB_SECT_XN_MASK (1 << 4) 505 #define TTB_SECT_C_MASK (1 << 3) 506 #define TTB_SECT_B_MASK (1 << 2) 507 #define TTB_SECT (2 << 0) 508 509 /* options available for data cache on each page */ 510 enum dcache_option { 511 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, 512 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, 513 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, 514 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), 515 }; 516 #else 517 #define TTB_SECT_AP (3 << 10) 518 /* options available for data cache on each page */ 519 enum dcache_option { 520 DCACHE_OFF = 0x12, 521 DCACHE_WRITETHROUGH = 0x1a, 522 DCACHE_WRITEBACK = 0x1e, 523 DCACHE_WRITEALLOC = 0x16, 524 }; 525 #endif 526 527 /* Size of an MMU section */ 528 enum { 529 #ifdef CONFIG_ARMV7_LPAE 530 MMU_SECTION_SHIFT = 21, /* 2MB */ 531 #else 532 MMU_SECTION_SHIFT = 20, /* 1MB */ 533 #endif 534 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 535 }; 536 537 #ifdef CONFIG_CPU_V7 538 /* TTBR0 bits */ 539 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 540 #define TTBR0_RGN_NC (0 << 3) 541 #define TTBR0_RGN_WBWA (1 << 3) 542 #define TTBR0_RGN_WT (2 << 3) 543 #define TTBR0_RGN_WB (3 << 3) 544 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ 545 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) 546 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) 547 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) 548 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) 549 #endif 550 551 /** 552 * Register an update to the page tables, and flush the TLB 553 * 554 * \param start start address of update in page table 555 * \param stop stop address of update in page table 556 */ 557 void mmu_page_table_flush(unsigned long start, unsigned long stop); 558 559 #endif /* __ASSEMBLY__ */ 560 561 #define arch_align_stack(x) (x) 562 563 #endif /* __KERNEL__ */ 564 565 #endif /* CONFIG_ARM64 */ 566 567 #ifndef __ASSEMBLY__ 568 /** 569 * save_boot_params() - Save boot parameters before starting reset sequence 570 * 571 * If you provide this function it will be called immediately U-Boot starts, 572 * both for SPL and U-Boot proper. 573 * 574 * All registers are unchanged from U-Boot entry. No registers need be 575 * preserved. 576 * 577 * This is not a normal C function. There is no stack. Return by branching to 578 * save_boot_params_ret. 579 * 580 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); 581 */ 582 583 /** 584 * save_boot_params_ret() - Return from save_boot_params() 585 * 586 * If you provide save_boot_params(), then you should jump back to this 587 * function when done. Try to preserve all registers. 588 * 589 * If your implementation of save_boot_params() is in C then it is acceptable 590 * to simply call save_boot_params_ret() at the end of your function. Since 591 * there is no link register set up, you cannot just exit the function. U-Boot 592 * will return to the (initialised) value of lr, and likely crash/hang. 593 * 594 * If your implementation of save_boot_params() is in assembler then you 595 * should use 'b' or 'bx' to return to save_boot_params_ret. 596 */ 597 void save_boot_params_ret(void); 598 599 /** 600 * Change the cache settings for a region. 601 * 602 * \param start start address of memory region to change 603 * \param size size of memory region to change 604 * \param option dcache option to select 605 */ 606 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, 607 enum dcache_option option); 608 609 #ifdef CONFIG_SYS_NONCACHED_MEMORY 610 void noncached_init(void); 611 phys_addr_t noncached_alloc(size_t size, size_t align); 612 #endif /* CONFIG_SYS_NONCACHED_MEMORY */ 613 614 #endif /* __ASSEMBLY__ */ 615 616 #endif 617