xref: /rk3399_rockchip-uboot/arch/arm/include/asm/psci.h (revision 2c774165449ebb180060b8596764140cfb00a1e1)
1ecf07a79SMarc Zyngier /*
2ecf07a79SMarc Zyngier  * Copyright (C) 2013 - ARM Ltd
3ecf07a79SMarc Zyngier  * Author: Marc Zyngier <marc.zyngier@arm.com>
4ecf07a79SMarc Zyngier  *
5ecf07a79SMarc Zyngier  * This program is free software; you can redistribute it and/or modify
6ecf07a79SMarc Zyngier  * it under the terms of the GNU General Public License version 2 as
7ecf07a79SMarc Zyngier  * published by the Free Software Foundation.
8ecf07a79SMarc Zyngier  *
9ecf07a79SMarc Zyngier  * This program is distributed in the hope that it will be useful,
10ecf07a79SMarc Zyngier  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11ecf07a79SMarc Zyngier  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12ecf07a79SMarc Zyngier  * GNU General Public License for more details.
13ecf07a79SMarc Zyngier  *
14ecf07a79SMarc Zyngier  * You should have received a copy of the GNU General Public License
15ecf07a79SMarc Zyngier  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16ecf07a79SMarc Zyngier  */
17ecf07a79SMarc Zyngier 
18ecf07a79SMarc Zyngier #ifndef __ARM_PSCI_H__
19ecf07a79SMarc Zyngier #define __ARM_PSCI_H__
20ecf07a79SMarc Zyngier 
21*2c774165SHou Zhiqiang #define ARM_PSCI_VER_1_0		(0x00010000)
22*2c774165SHou Zhiqiang #define ARM_PSCI_VER_0_2		(0x00000002)
23*2c774165SHou Zhiqiang 
245a07abb3SBeniamino Galvani /* PSCI 0.1 interface */
25ecf07a79SMarc Zyngier #define ARM_PSCI_FN_BASE		0x95c1ba5e
26ecf07a79SMarc Zyngier #define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
27ecf07a79SMarc Zyngier 
28ecf07a79SMarc Zyngier #define ARM_PSCI_FN_CPU_SUSPEND		ARM_PSCI_FN(0)
29ecf07a79SMarc Zyngier #define ARM_PSCI_FN_CPU_OFF		ARM_PSCI_FN(1)
30ecf07a79SMarc Zyngier #define ARM_PSCI_FN_CPU_ON		ARM_PSCI_FN(2)
31ecf07a79SMarc Zyngier #define ARM_PSCI_FN_MIGRATE		ARM_PSCI_FN(3)
32ecf07a79SMarc Zyngier 
33ecf07a79SMarc Zyngier #define ARM_PSCI_RET_SUCCESS		0
34ecf07a79SMarc Zyngier #define ARM_PSCI_RET_NI			(-1)
35ecf07a79SMarc Zyngier #define ARM_PSCI_RET_INVAL		(-2)
36ecf07a79SMarc Zyngier #define ARM_PSCI_RET_DENIED		(-3)
37116339d4SHongbo Zhang #define ARM_PSCI_RET_ALREADY_ON		(-4)
38116339d4SHongbo Zhang #define ARM_PSCI_RET_ON_PENDING		(-5)
39116339d4SHongbo Zhang #define ARM_PSCI_RET_INTERNAL_FAILURE	(-6)
40116339d4SHongbo Zhang #define ARM_PSCI_RET_NOT_PRESENT	(-7)
41116339d4SHongbo Zhang #define ARM_PSCI_RET_DISABLED		(-8)
42116339d4SHongbo Zhang #define ARM_PSCI_RET_INVALID_ADDRESS	(-9)
43ecf07a79SMarc Zyngier 
445a07abb3SBeniamino Galvani /* PSCI 0.2 interface */
455a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_BASE			0x84000000
465a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN(n)			(ARM_PSCI_0_2_FN_BASE + (n))
475a07abb3SBeniamino Galvani 
485a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_PSCI_VERSION		ARM_PSCI_0_2_FN(0)
495a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_CPU_SUSPEND		ARM_PSCI_0_2_FN(1)
505a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_CPU_OFF			ARM_PSCI_0_2_FN(2)
515a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_CPU_ON			ARM_PSCI_0_2_FN(3)
525a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_AFFINITY_INFO		ARM_PSCI_0_2_FN(4)
535a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_MIGRATE			ARM_PSCI_0_2_FN(5)
545a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE	ARM_PSCI_0_2_FN(6)
555a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN(7)
565a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_SYSTEM_OFF		ARM_PSCI_0_2_FN(8)
575a07abb3SBeniamino Galvani #define ARM_PSCI_0_2_FN_SYSTEM_RESET		ARM_PSCI_0_2_FN(9)
585a07abb3SBeniamino Galvani 
59116339d4SHongbo Zhang /* PSCI 1.0 interface */
60116339d4SHongbo Zhang #define ARM_PSCI_1_0_FN_PSCI_FEATURES		ARM_PSCI_0_2_FN(10)
61116339d4SHongbo Zhang #define ARM_PSCI_1_0_FN_CPU_FREEZE		ARM_PSCI_0_2_FN(11)
62116339d4SHongbo Zhang #define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND	ARM_PSCI_0_2_FN(12)
63116339d4SHongbo Zhang #define ARM_PSCI_1_0_FN_NODE_HW_STATE		ARM_PSCI_0_2_FN(13)
64116339d4SHongbo Zhang #define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND		ARM_PSCI_0_2_FN(14)
65116339d4SHongbo Zhang #define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE	ARM_PSCI_0_2_FN(15)
66116339d4SHongbo Zhang #define ARM_PSCI_1_0_FN_STAT_RESIDENCY		ARM_PSCI_0_2_FN(16)
67116339d4SHongbo Zhang #define ARM_PSCI_1_0_FN_STAT_COUNT		ARM_PSCI_0_2_FN(17)
68116339d4SHongbo Zhang 
69980d6a55SChen-Yu Tsai /* 1KB stack per core */
70980d6a55SChen-Yu Tsai #define ARM_PSCI_STACK_SHIFT	10
71980d6a55SChen-Yu Tsai #define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)
72980d6a55SChen-Yu Tsai 
737e742c27SHongbo Zhang /* PSCI affinity level state returned by AFFINITY_INFO */
747e742c27SHongbo Zhang #define PSCI_AFFINITY_LEVEL_ON		0
757e742c27SHongbo Zhang #define PSCI_AFFINITY_LEVEL_OFF		1
767e742c27SHongbo Zhang #define PSCI_AFFINITY_LEVEL_ON_PENDING	2
777e742c27SHongbo Zhang 
78dd09f7e7STom Rini #ifndef __ASSEMBLY__
79cbeeb2aeSChen-Yu Tsai #include <asm/types.h>
80cbeeb2aeSChen-Yu Tsai 
8145c334e6SChen-Yu Tsai /* These 2 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */
8245c334e6SChen-Yu Tsai u32 psci_get_target_pc(int cpu);
8345c334e6SChen-Yu Tsai void psci_save_target_pc(int cpu, u32 pc);
8445c334e6SChen-Yu Tsai 
85cbeeb2aeSChen-Yu Tsai void psci_cpu_entry(void);
86cbeeb2aeSChen-Yu Tsai u32 psci_get_cpu_id(void);
87cbeeb2aeSChen-Yu Tsai void psci_cpu_off_common(void);
88cbeeb2aeSChen-Yu Tsai 
89dd09f7e7STom Rini int psci_update_dt(void *fdt);
90ce416facSJan Kiszka void psci_board_init(void);
9145684ae3SHou Zhiqiang int fdt_psci(void *fdt);
92dd09f7e7STom Rini #endif /* ! __ASSEMBLY__ */
93dd09f7e7STom Rini 
94ecf07a79SMarc Zyngier #endif /* __ARM_PSCI_H__ */
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