1d2f18c27SAneesh V /* 2d2f18c27SAneesh V * (C) Copyright 2010 3d2f18c27SAneesh V * Texas Instruments, <www.ti.com> 4d2f18c27SAneesh V * 5d2f18c27SAneesh V * Aneesh V <aneesh@ti.com> 6d2f18c27SAneesh V * 7d2f18c27SAneesh V * See file CREDITS for list of people who contributed to this 8d2f18c27SAneesh V * project. 9d2f18c27SAneesh V * 10d2f18c27SAneesh V * This program is free software; you can redistribute it and/or 11d2f18c27SAneesh V * modify it under the terms of the GNU General Public License as 12d2f18c27SAneesh V * published by the Free Software Foundation; either version 2 of 13d2f18c27SAneesh V * the License, or (at your option) any later version. 14d2f18c27SAneesh V * 15d2f18c27SAneesh V * This program is distributed in the hope that it will be useful, 16d2f18c27SAneesh V * but WITHOUT ANY WARRANTY; without even the implied warranty of 17d2f18c27SAneesh V * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18d2f18c27SAneesh V * GNU General Public License for more details. 19d2f18c27SAneesh V * 20d2f18c27SAneesh V * You should have received a copy of the GNU General Public License 21d2f18c27SAneesh V * along with this program; if not, write to the Free Software 22d2f18c27SAneesh V * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23d2f18c27SAneesh V * MA 02111-1307 USA 24d2f18c27SAneesh V */ 25d2f18c27SAneesh V #ifndef _OMAP_COMMON_H_ 26d2f18c27SAneesh V #define _OMAP_COMMON_H_ 27d2f18c27SAneesh V 283776801dSAneesh V /* Max value for DPLL multiplier M */ 293776801dSAneesh V #define OMAP_DPLL_MAX_N 127 303776801dSAneesh V 31d2f18c27SAneesh V /* HW Init Context */ 32d2f18c27SAneesh V #define OMAP_INIT_CONTEXT_SPL 0 33d2f18c27SAneesh V #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 34d2f18c27SAneesh V #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 35d2f18c27SAneesh V #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 36d2f18c27SAneesh V 37bcae7211SAneesh V void preloader_console_init(void); 38bcae7211SAneesh V 398cf686e1SAneesh V /* Boot device */ 40508a58faSSricharan #ifdef CONFIG_OMAP54XX 41508a58faSSricharan #define BOOT_DEVICE_NONE 0 42508a58faSSricharan #define BOOT_DEVICE_XIP 1 43508a58faSSricharan #define BOOT_DEVICE_XIPWAIT 2 44508a58faSSricharan #define BOOT_DEVICE_NAND 3 45508a58faSSricharan #define BOOT_DEVICE_ONE_NAND 4 46508a58faSSricharan #define BOOT_DEVICE_MMC1 5 47508a58faSSricharan #define BOOT_DEVICE_MMC2 6 48508a58faSSricharan #define BOOT_DEVICE_MMC3 7 49508a58faSSricharan #elif defined(CONFIG_OMAP44XX) /* OMAP4 */ 508cf686e1SAneesh V #define BOOT_DEVICE_NONE 0 518cf686e1SAneesh V #define BOOT_DEVICE_XIP 1 528cf686e1SAneesh V #define BOOT_DEVICE_XIPWAIT 2 538cf686e1SAneesh V #define BOOT_DEVICE_NAND 3 548cf686e1SAneesh V #define BOOT_DEVICE_ONE_NAND 4 558cf686e1SAneesh V #define BOOT_DEVICE_MMC1 5 568cf686e1SAneesh V #define BOOT_DEVICE_MMC2 6 57d6cac9c8SSandeep Paulraj #elif defined(CONFIG_OMAP34XX) /* OMAP3 */ 58bb085b87SSimon Schwarz #define BOOT_DEVICE_NONE 0 59bb085b87SSimon Schwarz #define BOOT_DEVICE_XIP 1 60bb085b87SSimon Schwarz #define BOOT_DEVICE_NAND 2 61bb085b87SSimon Schwarz #define BOOT_DEVICE_ONE_NAND 3 62bb085b87SSimon Schwarz #define BOOT_DEVICE_MMC2 5 /*emmc*/ 63bb085b87SSimon Schwarz #define BOOT_DEVICE_MMC1 6 64bb085b87SSimon Schwarz #define BOOT_DEVICE_XIPWAIT 7 65bb085b87SSimon Schwarz #endif 668cf686e1SAneesh V 678cf686e1SAneesh V /* Boot type */ 688cf686e1SAneesh V #define MMCSD_MODE_UNDEFINED 0 698cf686e1SAneesh V #define MMCSD_MODE_RAW 1 708cf686e1SAneesh V #define MMCSD_MODE_FAT 2 71bb085b87SSimon Schwarz #define NAND_MODE_HW_ECC 3 72bb085b87SSimon Schwarz 73bb085b87SSimon Schwarz struct spl_image_info { 74bb085b87SSimon Schwarz const char *name; 75bb085b87SSimon Schwarz u8 os; 76bb085b87SSimon Schwarz u32 load_addr; 77bb085b87SSimon Schwarz u32 entry_point; 78bb085b87SSimon Schwarz u32 size; 79bb085b87SSimon Schwarz }; 80bb085b87SSimon Schwarz 81bb085b87SSimon Schwarz extern struct spl_image_info spl_image; 828cf686e1SAneesh V 8378f455c0SSricharan extern u32* boot_params_ptr; 848cf686e1SAneesh V u32 omap_boot_device(void); 858cf686e1SAneesh V u32 omap_boot_mode(void); 868cf686e1SAneesh V 87bb085b87SSimon Schwarz /* SPL common function s*/ 88bb085b87SSimon Schwarz void spl_parse_image_header(const struct image_header *header); 89cc3f7058STom Rini void omap_rev_string(char *omap_rev_string); 90bb085b87SSimon Schwarz 91bb085b87SSimon Schwarz /* NAND SPL functions */ 92bb085b87SSimon Schwarz void spl_nand_load_image(void); 93bb085b87SSimon Schwarz 94bb085b87SSimon Schwarz /* MMC SPL functions */ 95bb085b87SSimon Schwarz void spl_mmc_load_image(void); 96bb085b87SSimon Schwarz 97*ee08a826STom Rini #ifdef CONFIG_SPL_BOARD_INIT 98*ee08a826STom Rini void spl_board_init(void); 99*ee08a826STom Rini #endif 100*ee08a826STom Rini 101508a58faSSricharan /* 102508a58faSSricharan * silicon revisions. 103508a58faSSricharan * Moving this to common, so that most of code can be moved to common, 104508a58faSSricharan * directories. 105508a58faSSricharan */ 106508a58faSSricharan 107508a58faSSricharan /* omap4 */ 108508a58faSSricharan #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF 109508a58faSSricharan #define OMAP4430_ES1_0 0x44300100 110508a58faSSricharan #define OMAP4430_ES2_0 0x44300200 111508a58faSSricharan #define OMAP4430_ES2_1 0x44300210 112508a58faSSricharan #define OMAP4430_ES2_2 0x44300220 113508a58faSSricharan #define OMAP4430_ES2_3 0x44300230 114508a58faSSricharan #define OMAP4460_ES1_0 0x44600100 1159404758eSAneesh V #define OMAP4460_ES1_1 0x44600110 116508a58faSSricharan 117508a58faSSricharan /* omap5 */ 118508a58faSSricharan #define OMAP5430_SILICON_ID_INVALID 0 119508a58faSSricharan #define OMAP5430_ES1_0 0x54300100 120d2f18c27SAneesh V #endif /* _OMAP_COMMON_H_ */ 121