1d2f18c27SAneesh V /* 2d2f18c27SAneesh V * (C) Copyright 2010 3d2f18c27SAneesh V * Texas Instruments, <www.ti.com> 4d2f18c27SAneesh V * 5d2f18c27SAneesh V * Aneesh V <aneesh@ti.com> 6d2f18c27SAneesh V * 7d2f18c27SAneesh V * See file CREDITS for list of people who contributed to this 8d2f18c27SAneesh V * project. 9d2f18c27SAneesh V * 10d2f18c27SAneesh V * This program is free software; you can redistribute it and/or 11d2f18c27SAneesh V * modify it under the terms of the GNU General Public License as 12d2f18c27SAneesh V * published by the Free Software Foundation; either version 2 of 13d2f18c27SAneesh V * the License, or (at your option) any later version. 14d2f18c27SAneesh V * 15d2f18c27SAneesh V * This program is distributed in the hope that it will be useful, 16d2f18c27SAneesh V * but WITHOUT ANY WARRANTY; without even the implied warranty of 17d2f18c27SAneesh V * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18d2f18c27SAneesh V * GNU General Public License for more details. 19d2f18c27SAneesh V * 20d2f18c27SAneesh V * You should have received a copy of the GNU General Public License 21d2f18c27SAneesh V * along with this program; if not, write to the Free Software 22d2f18c27SAneesh V * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23d2f18c27SAneesh V * MA 02111-1307 USA 24d2f18c27SAneesh V */ 25d2f18c27SAneesh V #ifndef _OMAP_COMMON_H_ 26d2f18c27SAneesh V #define _OMAP_COMMON_H_ 27d2f18c27SAneesh V 283776801dSAneesh V /* Max value for DPLL multiplier M */ 293776801dSAneesh V #define OMAP_DPLL_MAX_N 127 303776801dSAneesh V 31d2f18c27SAneesh V /* HW Init Context */ 32d2f18c27SAneesh V #define OMAP_INIT_CONTEXT_SPL 0 33d2f18c27SAneesh V #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 34d2f18c27SAneesh V #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 35d2f18c27SAneesh V #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 36d2f18c27SAneesh V 37bcae7211SAneesh V void preloader_console_init(void); 38bcae7211SAneesh V 398cf686e1SAneesh V /* Boot device */ 40508a58faSSricharan #ifdef CONFIG_OMAP54XX 41508a58faSSricharan #define BOOT_DEVICE_NONE 0 42508a58faSSricharan #define BOOT_DEVICE_XIP 1 43508a58faSSricharan #define BOOT_DEVICE_XIPWAIT 2 44508a58faSSricharan #define BOOT_DEVICE_NAND 3 45508a58faSSricharan #define BOOT_DEVICE_ONE_NAND 4 46508a58faSSricharan #define BOOT_DEVICE_MMC1 5 47508a58faSSricharan #define BOOT_DEVICE_MMC2 6 48f75231b7SBalaji T K #define BOOT_DEVICE_MMC2_2 7 49508a58faSSricharan #elif defined(CONFIG_OMAP44XX) /* OMAP4 */ 508cf686e1SAneesh V #define BOOT_DEVICE_NONE 0 518cf686e1SAneesh V #define BOOT_DEVICE_XIP 1 528cf686e1SAneesh V #define BOOT_DEVICE_XIPWAIT 2 538cf686e1SAneesh V #define BOOT_DEVICE_NAND 3 548cf686e1SAneesh V #define BOOT_DEVICE_ONE_NAND 4 558cf686e1SAneesh V #define BOOT_DEVICE_MMC1 5 568cf686e1SAneesh V #define BOOT_DEVICE_MMC2 6 57f75231b7SBalaji T K #define BOOT_DEVICE_MMC2_2 0xFF 58d6cac9c8SSandeep Paulraj #elif defined(CONFIG_OMAP34XX) /* OMAP3 */ 59bb085b87SSimon Schwarz #define BOOT_DEVICE_NONE 0 60bb085b87SSimon Schwarz #define BOOT_DEVICE_XIP 1 61bb085b87SSimon Schwarz #define BOOT_DEVICE_NAND 2 62bb085b87SSimon Schwarz #define BOOT_DEVICE_ONE_NAND 3 63bb085b87SSimon Schwarz #define BOOT_DEVICE_MMC2 5 /*emmc*/ 64bb085b87SSimon Schwarz #define BOOT_DEVICE_MMC1 6 65bb085b87SSimon Schwarz #define BOOT_DEVICE_XIPWAIT 7 66f75231b7SBalaji T K #define BOOT_DEVICE_MMC2_2 0xFF 678a8f084eSChandan Nath #elif defined(CONFIG_AM33XX) /* AM33XX */ 688a8f084eSChandan Nath #define BOOT_DEVICE_NAND 5 698a8f084eSChandan Nath #define BOOT_DEVICE_MMC1 8 708a8f084eSChandan Nath #define BOOT_DEVICE_MMC2 0 718a8f084eSChandan Nath #define BOOT_DEVICE_UART 65 72f75231b7SBalaji T K #define BOOT_DEVICE_MMC2_2 0xFF 73bb085b87SSimon Schwarz #endif 748cf686e1SAneesh V 758cf686e1SAneesh V /* Boot type */ 768cf686e1SAneesh V #define MMCSD_MODE_UNDEFINED 0 778cf686e1SAneesh V #define MMCSD_MODE_RAW 1 788cf686e1SAneesh V #define MMCSD_MODE_FAT 2 79bb085b87SSimon Schwarz #define NAND_MODE_HW_ECC 3 80bb085b87SSimon Schwarz 81bb085b87SSimon Schwarz struct spl_image_info { 82bb085b87SSimon Schwarz const char *name; 83bb085b87SSimon Schwarz u8 os; 84bb085b87SSimon Schwarz u32 load_addr; 85bb085b87SSimon Schwarz u32 entry_point; 86bb085b87SSimon Schwarz u32 size; 87bb085b87SSimon Schwarz }; 88bb085b87SSimon Schwarz 89bb085b87SSimon Schwarz extern struct spl_image_info spl_image; 908cf686e1SAneesh V 9178f455c0SSricharan extern u32* boot_params_ptr; 928cf686e1SAneesh V u32 omap_boot_device(void); 938cf686e1SAneesh V u32 omap_boot_mode(void); 948cf686e1SAneesh V 95bb085b87SSimon Schwarz /* SPL common function s*/ 96bb085b87SSimon Schwarz void spl_parse_image_header(const struct image_header *header); 97761ca31eSAndreas Müller void omap_rev_string(void); 989e70c08bSSimon Schwarz void spl_board_prepare_for_linux(void); 99379c19abSSimon Schwarz int spl_start_uboot(void); 100bb085b87SSimon Schwarz 101bb085b87SSimon Schwarz /* NAND SPL functions */ 102bb085b87SSimon Schwarz void spl_nand_load_image(void); 103bb085b87SSimon Schwarz 104bb085b87SSimon Schwarz /* MMC SPL functions */ 105bb085b87SSimon Schwarz void spl_mmc_load_image(void); 106bb085b87SSimon Schwarz 10724de357aSMatt Porter /* YMODEM SPL functions */ 10824de357aSMatt Porter void spl_ymodem_load_image(void); 10924de357aSMatt Porter 110ee08a826STom Rini #ifdef CONFIG_SPL_BOARD_INIT 111ee08a826STom Rini void spl_board_init(void); 112ee08a826STom Rini #endif 113ee08a826STom Rini 114087189fbSSRICHARAN R static inline u32 omap_revision(void) 115087189fbSSRICHARAN R { 116087189fbSSRICHARAN R extern u32 *const omap_si_rev; 117087189fbSSRICHARAN R return *omap_si_rev; 118087189fbSSRICHARAN R } 119087189fbSSRICHARAN R 120508a58faSSricharan /* 121508a58faSSricharan * silicon revisions. 122508a58faSSricharan * Moving this to common, so that most of code can be moved to common, 123508a58faSSricharan * directories. 124508a58faSSricharan */ 125508a58faSSricharan 126508a58faSSricharan /* omap4 */ 127508a58faSSricharan #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF 128508a58faSSricharan #define OMAP4430_ES1_0 0x44300100 129508a58faSSricharan #define OMAP4430_ES2_0 0x44300200 130508a58faSSricharan #define OMAP4430_ES2_1 0x44300210 131508a58faSSricharan #define OMAP4430_ES2_2 0x44300220 132508a58faSSricharan #define OMAP4430_ES2_3 0x44300230 133508a58faSSricharan #define OMAP4460_ES1_0 0x44600100 1349404758eSAneesh V #define OMAP4460_ES1_1 0x44600110 135508a58faSSricharan 136508a58faSSricharan /* omap5 */ 137508a58faSSricharan #define OMAP5430_SILICON_ID_INVALID 0 138508a58faSSricharan #define OMAP5430_ES1_0 0x54300100 139*0a0bf7b2SLokesh Vutla #define OMAP5432_ES1_0 0x54320100 140d2f18c27SAneesh V #endif /* _OMAP_COMMON_H_ */ 141