1*552a848eSStefano Babic /* 2*552a848eSStefano Babic * Copyright (C) 2015 Freescale Semiconductor, Inc. 3*552a848eSStefano Babic * 4*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+ 5*552a848eSStefano Babic */ 6*552a848eSStefano Babic 7*552a848eSStefano Babic #ifndef _ASM_ARCH_SYSTEM_COUNTER_H 8*552a848eSStefano Babic #define _ASM_ARCH_SYSTEM_COUNTER_H 9*552a848eSStefano Babic 10*552a848eSStefano Babic /* System Counter */ 11*552a848eSStefano Babic struct sctr_regs { 12*552a848eSStefano Babic u32 cntcr; 13*552a848eSStefano Babic u32 cntsr; 14*552a848eSStefano Babic u32 cntcv1; 15*552a848eSStefano Babic u32 cntcv2; 16*552a848eSStefano Babic u32 resv1[4]; 17*552a848eSStefano Babic u32 cntfid0; 18*552a848eSStefano Babic u32 cntfid1; 19*552a848eSStefano Babic u32 cntfid2; 20*552a848eSStefano Babic u32 resv2[1001]; 21*552a848eSStefano Babic u32 counterid[1]; 22*552a848eSStefano Babic }; 23*552a848eSStefano Babic 24*552a848eSStefano Babic #define SC_CNTCR_ENABLE (1 << 0) 25*552a848eSStefano Babic #define SC_CNTCR_HDBG (1 << 1) 26*552a848eSStefano Babic #define SC_CNTCR_FREQ0 (1 << 8) 27*552a848eSStefano Babic #define SC_CNTCR_FREQ1 (1 << 9) 28*552a848eSStefano Babic 29*552a848eSStefano Babic #endif 30