xref: /rk3399_rockchip-uboot/arch/arm/include/asm/mach-imx/regs-usbphy.h (revision 39632b4a01210e329333d787d828157dcd2c7328)
1*552a848eSStefano Babic /*
2*552a848eSStefano Babic  * Freescale USB PHY Register Definitions
3*552a848eSStefano Babic  *
4*552a848eSStefano Babic  * SPDX-License-Identifier: GPL-2.0+
5*552a848eSStefano Babic  *
6*552a848eSStefano Babic  */
7*552a848eSStefano Babic 
8*552a848eSStefano Babic #ifndef __REGS_USBPHY_H__
9*552a848eSStefano Babic #define __REGS_USBPHY_H__
10*552a848eSStefano Babic 
11*552a848eSStefano Babic #define USBPHY_CTRL						0x00000030
12*552a848eSStefano Babic #define USBPHY_CTRL_SET					0x00000034
13*552a848eSStefano Babic #define USBPHY_CTRL_CLR					0x00000038
14*552a848eSStefano Babic #define USBPHY_CTRL_TOG					0x0000003C
15*552a848eSStefano Babic #define USBPHY_PWD						0x00000000
16*552a848eSStefano Babic #define USBPHY_TX						0x00000010
17*552a848eSStefano Babic #define USBPHY_RX						0x00000020
18*552a848eSStefano Babic #define USBPHY_DEBUG					0x00000050
19*552a848eSStefano Babic 
20*552a848eSStefano Babic #define USBPHY_CTRL_ENUTMILEVEL2		(1 << 14)
21*552a848eSStefano Babic #define USBPHY_CTRL_ENUTMILEVEL3		(1 << 15)
22*552a848eSStefano Babic #define USBPHY_CTRL_OTG_ID				(1 << 27)
23*552a848eSStefano Babic #define USBPHY_CTRL_CLKGATE				(1 << 30)
24*552a848eSStefano Babic #define USBPHY_CTRL_SFTRST				(1 << 31)
25*552a848eSStefano Babic 
26*552a848eSStefano Babic #endif /* __REGS_USBPHY_H__ */
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