1*552a848eSStefano Babic /* 2*552a848eSStefano Babic * Copyright (C) 2016 Freescale Semiconductor, Inc. 3*552a848eSStefano Babic * 4*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+ 5*552a848eSStefano Babic */ 6*552a848eSStefano Babic 7*552a848eSStefano Babic #ifndef __RDC_SEMA_H__ 8*552a848eSStefano Babic #define __RDC_SEMA_H__ 9*552a848eSStefano Babic 10*552a848eSStefano Babic /* 11*552a848eSStefano Babic * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout. 12*552a848eSStefano Babic * 13*552a848eSStefano Babic * [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ] 14*552a848eSStefano Babic * d3 d2 d1 d0 | master id | peri id 15*552a848eSStefano Babic * d[x] means domain[x], x can be [3 - 0]. 16*552a848eSStefano Babic */ 17*552a848eSStefano Babic typedef u32 rdc_peri_cfg_t; 18*552a848eSStefano Babic typedef u32 rdc_ma_cfg_t; 19*552a848eSStefano Babic 20*552a848eSStefano Babic #define RDC_PERI_SHIFT 0 21*552a848eSStefano Babic #define RDC_PERI_MASK 0xFF 22*552a848eSStefano Babic 23*552a848eSStefano Babic #define RDC_DOMAIN_SHIFT_BASE 16 24*552a848eSStefano Babic #define RDC_DOMAIN_MASK 0xFF0000 25*552a848eSStefano Babic #define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1))) 26*552a848eSStefano Babic #define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x))) 27*552a848eSStefano Babic 28*552a848eSStefano Babic #define RDC_MASTER_SHIFT 8 29*552a848eSStefano Babic #define RDC_MASTER_MASK 0xFF00 30*552a848eSStefano Babic #define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \ 31*552a848eSStefano Babic (domain_id << RDC_DOMAIN_SHIFT_BASE)) 32*552a848eSStefano Babic 33*552a848eSStefano Babic /* The Following macro definitions are common to i.MX6SX and i.MX7D */ 34*552a848eSStefano Babic #define SEMA_GATES_NUM 64 35*552a848eSStefano Babic 36*552a848eSStefano Babic #define RDC_MDA_DID_SHIFT 0 37*552a848eSStefano Babic #define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT) 38*552a848eSStefano Babic #define RDC_MDA_LCK_SHIFT 31 39*552a848eSStefano Babic #define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT) 40*552a848eSStefano Babic 41*552a848eSStefano Babic #define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1) 42*552a848eSStefano Babic #define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain)) 43*552a848eSStefano Babic #define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain)) 44*552a848eSStefano Babic #define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain)) 45*552a848eSStefano Babic #define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \ 46*552a848eSStefano Babic RDC_PDAP_DR_MASK(domain)) 47*552a848eSStefano Babic 48*552a848eSStefano Babic #define RDC_PDAP_SREQ_SHIFT 30 49*552a848eSStefano Babic #define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT) 50*552a848eSStefano Babic #define RDC_PDAP_LCK_SHIFT 31 51*552a848eSStefano Babic #define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT) 52*552a848eSStefano Babic 53*552a848eSStefano Babic #define RDC_MRSA_SADR_SHIFT 7 54*552a848eSStefano Babic #define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT) 55*552a848eSStefano Babic 56*552a848eSStefano Babic #define RDC_MREA_EADR_SHIFT 7 57*552a848eSStefano Babic #define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT) 58*552a848eSStefano Babic 59*552a848eSStefano Babic #define RDC_MRC_DW_SHIFT(domain) (domain) 60*552a848eSStefano Babic #define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain)) 61*552a848eSStefano Babic #define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain)) 62*552a848eSStefano Babic #define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain)) 63*552a848eSStefano Babic #define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \ 64*552a848eSStefano Babic RDC_MRC_DR_MASK(domain)) 65*552a848eSStefano Babic #define RDC_MRC_ENA_SHIFT 30 66*552a848eSStefano Babic #define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT) 67*552a848eSStefano Babic #define RDC_MRC_LCK_SHIFT 31 68*552a848eSStefano Babic #define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT) 69*552a848eSStefano Babic 70*552a848eSStefano Babic #define RDC_MRVS_VDID_SHIFT 0 71*552a848eSStefano Babic #define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT) 72*552a848eSStefano Babic #define RDC_MRVS_AD_SHIFT 4 73*552a848eSStefano Babic #define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT) 74*552a848eSStefano Babic #define RDC_MRVS_VADDR_SHIFT 5 75*552a848eSStefano Babic #define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT) 76*552a848eSStefano Babic 77*552a848eSStefano Babic #define RDC_SEMA_GATE_GTFSM_SHIFT 0 78*552a848eSStefano Babic #define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT) 79*552a848eSStefano Babic #define RDC_SEMA_GATE_LDOM_SHIFT 5 80*552a848eSStefano Babic #define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT) 81*552a848eSStefano Babic 82*552a848eSStefano Babic #define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0 83*552a848eSStefano Babic #define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT) 84*552a848eSStefano Babic #define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2 85*552a848eSStefano Babic #define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT) 86*552a848eSStefano Babic #define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4 87*552a848eSStefano Babic #define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT) 88*552a848eSStefano Babic #define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8 89*552a848eSStefano Babic #define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT) 90*552a848eSStefano Babic 91*552a848eSStefano Babic int imx_rdc_check_permission(int per_id, int dom_id); 92*552a848eSStefano Babic int imx_rdc_sema_lock(int per_id); 93*552a848eSStefano Babic int imx_rdc_sema_unlock(int per_id); 94*552a848eSStefano Babic int imx_rdc_setup_peri(rdc_peri_cfg_t p); 95*552a848eSStefano Babic int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list, 96*552a848eSStefano Babic unsigned count); 97*552a848eSStefano Babic int imx_rdc_setup_ma(rdc_ma_cfg_t p); 98*552a848eSStefano Babic int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count); 99*552a848eSStefano Babic 100*552a848eSStefano Babic #endif /* __RDC_SEMA_H__*/ 101