1*0ae76531SDavid Feng #ifndef __GIC_H__ 2*0ae76531SDavid Feng #define __GIC_H__ 316212b59SAndre Przywara 4*0ae76531SDavid Feng /* Register offsets for the ARM generic interrupt controller (GIC) */ 516212b59SAndre Przywara 616212b59SAndre Przywara #define GIC_DIST_OFFSET 0x1000 716212b59SAndre Przywara #define GIC_CPU_OFFSET_A9 0x0100 816212b59SAndre Przywara #define GIC_CPU_OFFSET_A15 0x2000 9*0ae76531SDavid Feng 10*0ae76531SDavid Feng /* Distributor Registers */ 11*0ae76531SDavid Feng #define GICD_CTLR 0x0000 12*0ae76531SDavid Feng #define GICD_TYPER 0x0004 13*0ae76531SDavid Feng #define GICD_IIDR 0x0008 14*0ae76531SDavid Feng #define GICD_STATUSR 0x0010 15*0ae76531SDavid Feng #define GICD_SETSPI_NSR 0x0040 16*0ae76531SDavid Feng #define GICD_CLRSPI_NSR 0x0048 17*0ae76531SDavid Feng #define GICD_SETSPI_SR 0x0050 18*0ae76531SDavid Feng #define GICD_CLRSPI_SR 0x0058 19*0ae76531SDavid Feng #define GICD_SEIR 0x0068 20*0ae76531SDavid Feng #define GICD_IGROUPRn 0x0080 21*0ae76531SDavid Feng #define GICD_ISENABLERn 0x0100 22*0ae76531SDavid Feng #define GICD_ICENABLERn 0x0180 23*0ae76531SDavid Feng #define GICD_ISPENDRn 0x0200 24*0ae76531SDavid Feng #define GICD_ICPENDRn 0x0280 25*0ae76531SDavid Feng #define GICD_ISACTIVERn 0x0300 26*0ae76531SDavid Feng #define GICD_ICACTIVERn 0x0380 27*0ae76531SDavid Feng #define GICD_IPRIORITYRn 0x0400 28*0ae76531SDavid Feng #define GICD_ITARGETSRn 0x0800 29*0ae76531SDavid Feng #define GICD_ICFGR 0x0c00 30*0ae76531SDavid Feng #define GICD_IGROUPMODRn 0x0d00 31*0ae76531SDavid Feng #define GICD_NSACRn 0x0e00 32*0ae76531SDavid Feng #define GICD_SGIR 0x0f00 33*0ae76531SDavid Feng #define GICD_CPENDSGIRn 0x0f10 34*0ae76531SDavid Feng #define GICD_SPENDSGIRn 0x0f20 35*0ae76531SDavid Feng #define GICD_IROUTERn 0x6000 36*0ae76531SDavid Feng 37*0ae76531SDavid Feng /* Cpu Interface Memory Mapped Registers */ 3816212b59SAndre Przywara #define GICC_CTLR 0x0000 3916212b59SAndre Przywara #define GICC_PMR 0x0004 40*0ae76531SDavid Feng #define GICC_BPR 0x0008 41ba6a1698SAndre Przywara #define GICC_IAR 0x000C 42ba6a1698SAndre Przywara #define GICC_EOIR 0x0010 43*0ae76531SDavid Feng #define GICC_RPR 0x0014 44*0ae76531SDavid Feng #define GICC_HPPIR 0x0018 45*0ae76531SDavid Feng #define GICC_ABPR 0x001c 46*0ae76531SDavid Feng #define GICC_AIAR 0x0020 47*0ae76531SDavid Feng #define GICC_AEOIR 0x0024 48*0ae76531SDavid Feng #define GICC_AHPPIR 0x0028 49*0ae76531SDavid Feng #define GICC_APRn 0x00d0 50*0ae76531SDavid Feng #define GICC_NSAPRn 0x00e0 51*0ae76531SDavid Feng #define GICC_IIDR 0x00fc 52*0ae76531SDavid Feng #define GICC_DIR 0x1000 5316212b59SAndre Przywara 54*0ae76531SDavid Feng #endif /* __GIC_H__ */ 55