198cb0efdSgaurav rana /* 298cb0efdSgaurav rana * Copyright 2015 Freescale Semiconductor, Inc. 398cb0efdSgaurav rana * 498cb0efdSgaurav rana * SPDX-License-Identifier: GPL-2.0+ 598cb0efdSgaurav rana */ 698cb0efdSgaurav rana 798cb0efdSgaurav rana #ifndef __FSL_SECURE_BOOT_H 898cb0efdSgaurav rana #define __FSL_SECURE_BOOT_H 998cb0efdSgaurav rana 10bdc22074SAneesh Bansal #ifdef CONFIG_CHAIN_OF_TRUST 112ed948f4SAneesh Bansal #define CONFIG_CMD_ESBC_VALIDATE 122ed948f4SAneesh Bansal #define CONFIG_FSL_SEC_MON 13fcfdb6d5SSaksham Jain #define CONFIG_SHA_HW_ACCEL 142ed948f4SAneesh Bansal #define CONFIG_SHA_PROG_HW_ACCEL 152ed948f4SAneesh Bansal 16028ac8c7SSumit Garg #define CONFIG_SPL_BOARD_INIT 17b63f8a43SSimon Glass #ifdef CONFIG_SPL_BUILD 18028ac8c7SSumit Garg /* 19028ac8c7SSumit Garg * Define the key hash for U-Boot here if public/private key pair used to 20028ac8c7SSumit Garg * sign U-boot are different from the SRK hash put in the fuse 21028ac8c7SSumit Garg * Example of defining KEY_HASH is 22028ac8c7SSumit Garg * #define CONFIG_SPL_UBOOT_KEY_HASH \ 23028ac8c7SSumit Garg * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 24028ac8c7SSumit Garg * else leave it defined as NULL 25028ac8c7SSumit Garg */ 26028ac8c7SSumit Garg 27028ac8c7SSumit Garg #define CONFIG_SPL_UBOOT_KEY_HASH NULL 28028ac8c7SSumit Garg #endif /* ifdef CONFIG_SPL_BUILD */ 29028ac8c7SSumit Garg 30028ac8c7SSumit Garg #ifndef CONFIG_SPL_BUILD 31028ac8c7SSumit Garg #define CONFIG_CMD_BLOB 32028ac8c7SSumit Garg #define CONFIG_CMD_HASH 332ed948f4SAneesh Bansal #define CONFIG_KEY_REVOCATION 342ed948f4SAneesh Bansal #ifndef CONFIG_SYS_RAMBOOT 352ed948f4SAneesh Bansal /* The key used for verification of next level images 362ed948f4SAneesh Bansal * is picked up from an Extension Table which has 372ed948f4SAneesh Bansal * been verified by the ISBC (Internal Secure boot Code) 382ed948f4SAneesh Bansal * in boot ROM of the SoC. 392ed948f4SAneesh Bansal * The feature is only applicable in case of NOR boot and is 402ed948f4SAneesh Bansal * not applicable in case of RAMBOOT (NAND, SD, SPI). 41ac55dadbSUdit Agarwal * For LS, this feature is available for all device if IE Table 42ac55dadbSUdit Agarwal * is copied to XIP memory 43ac55dadbSUdit Agarwal * Also, for LS, ISBC doesn't verify this table. 442ed948f4SAneesh Bansal */ 452ed948f4SAneesh Bansal #define CONFIG_FSL_ISBC_KEY_EXT 462ed948f4SAneesh Bansal 47fd6dbc98SSaksham Jain #endif 48fd6dbc98SSaksham Jain 49b3635f57SVinitha Pillai-B57223 #if defined(CONFIG_FSL_LAYERSCAPE) 50b3635f57SVinitha Pillai-B57223 /* 51b3635f57SVinitha Pillai-B57223 * For fsl layerscape based platforms, ESBC image Address in Header 52b3635f57SVinitha Pillai-B57223 * is 64 bit. 53fcfdb6d5SSaksham Jain */ 54ef6c55a2SAneesh Bansal #define CONFIG_ESBC_ADDR_64BIT 55ef6c55a2SAneesh Bansal #endif 56ef6c55a2SAneesh Bansal 573c1d218aSYork Sun #ifdef CONFIG_LS2080A 58bef238cbSSaksham Jain #define CONFIG_EXTRA_ENV \ 59bef238cbSSaksham Jain "setenv fdt_high 0xa0000000;" \ 60bef238cbSSaksham Jain "setenv initrd_high 0xcfffffff;" \ 61bef238cbSSaksham Jain "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 62bef238cbSSaksham Jain #else 6398cb0efdSgaurav rana #define CONFIG_EXTRA_ENV \ 6469d4b48cSSumit Garg "setenv fdt_high 0xffffffff;" \ 6569d4b48cSSumit Garg "setenv initrd_high 0xffffffff;" \ 6698cb0efdSgaurav rana "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 67bef238cbSSaksham Jain #endif 6898cb0efdSgaurav rana 693f701cc5SSaksham Jain /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from 703f701cc5SSaksham Jain * Non-XIP Memory (Nand/SD)*/ 7139199356SUdit Agarwal #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ 7269d4b48cSSumit Garg defined(CONFIG_SD_BOOT) 733f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_COPY_RAM 743f701cc5SSaksham Jain #endif 7569d4b48cSSumit Garg /* The address needs to be modified according to NOR, NAND, SD and 7669d4b48cSSumit Garg * DDR memory map 7769d4b48cSSumit Garg */ 7839199356SUdit Agarwal #ifdef CONFIG_FSL_LSCH3 7939199356SUdit Agarwal #define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 8039199356SUdit Agarwal #define CONFIG_BS_ADDR_DEVICE 0x580e00000 8139199356SUdit Agarwal #define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 8239199356SUdit Agarwal #define CONFIG_BS_ADDR_RAM 0xa0e00000 8369d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00002000 8469d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00001000 85216e93a1SSaksham Jain #else 8669d4b48cSSumit Garg #ifdef CONFIG_SD_BOOT 8769d4b48cSSumit Garg /* For SD boot address and size are assigned in terms of sector 8869d4b48cSSumit Garg * offset and no. of sectors respectively. 8969d4b48cSSumit Garg */ 909b6639faSVinitha Pillai #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 919b6639faSVinitha Pillai #define CONFIG_BS_ADDR_DEVICE 0x00000940 9269d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00000010 9369d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00000008 94b3635f57SVinitha Pillai-B57223 #elif defined(CONFIG_QSPI_BOOT) 95b3635f57SVinitha Pillai-B57223 #ifdef CONFIG_ARCH_LS1046A 96b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000 97b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_ADDR_DEVICE 0x40800000 98*d2a99502SVinitha Pillai-B57223 #elif defined(CONFIG_ARCH_LS1012A) 99*d2a99502SVinitha Pillai-B57223 #define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000 100*d2a99502SVinitha Pillai-B57223 #define CONFIG_BS_ADDR_DEVICE 0x40060000 10169d4b48cSSumit Garg #else 102b3635f57SVinitha Pillai-B57223 #error "Platform not supported" 103b3635f57SVinitha Pillai-B57223 #endif 104b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_HDR_SIZE 0x00002000 105b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_SIZE 0x00001000 106b3635f57SVinitha Pillai-B57223 #else /* Default NOR Boot */ 10769d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 10869d4b48cSSumit Garg #define CONFIG_BS_ADDR_DEVICE 0x60060000 10969d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00002000 11069d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00001000 111b3635f57SVinitha Pillai-B57223 #endif 11269d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_RAM 0x81000000 11369d4b48cSSumit Garg #define CONFIG_BS_ADDR_RAM 0x81020000 1143f701cc5SSaksham Jain #endif 1153f701cc5SSaksham Jain 1163f701cc5SSaksham Jain #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 1173f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 1183f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM 1193f701cc5SSaksham Jain #else 12069d4b48cSSumit Garg #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE 12169d4b48cSSumit Garg /* BOOTSCRIPT_ADDR is not required */ 122216e93a1SSaksham Jain #endif 12398cb0efdSgaurav rana 12407806e62SSumit Garg #ifdef CONFIG_FSL_LS_PPA 12507806e62SSumit Garg /* Define the key hash here if SRK used for signing PPA image is 12607806e62SSumit Garg * different from SRK hash put in SFP used for U-Boot. 12707806e62SSumit Garg * Example 128d1a795acSVinitha Pillai-B57223 * #define PPA_KEY_HASH \ 12907806e62SSumit Garg * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 13007806e62SSumit Garg */ 131d1a795acSVinitha Pillai-B57223 #define PPA_KEY_HASH NULL 13207806e62SSumit Garg #endif /* ifdef CONFIG_FSL_LS_PPA */ 13307806e62SSumit Garg 134bdc22074SAneesh Bansal #include <config_fsl_chain_trust.h> 135028ac8c7SSumit Garg #endif /* #ifndef CONFIG_SPL_BUILD */ 136bdc22074SAneesh Bansal #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 13798cb0efdSgaurav rana #endif 138