198cb0efdSgaurav rana /* 298cb0efdSgaurav rana * Copyright 2015 Freescale Semiconductor, Inc. 398cb0efdSgaurav rana * 498cb0efdSgaurav rana * SPDX-License-Identifier: GPL-2.0+ 598cb0efdSgaurav rana */ 698cb0efdSgaurav rana 798cb0efdSgaurav rana #ifndef __FSL_SECURE_BOOT_H 898cb0efdSgaurav rana #define __FSL_SECURE_BOOT_H 998cb0efdSgaurav rana 10bdc22074SAneesh Bansal #ifdef CONFIG_CHAIN_OF_TRUST 112ed948f4SAneesh Bansal #define CONFIG_CMD_ESBC_VALIDATE 122ed948f4SAneesh Bansal #define CONFIG_FSL_SEC_MON 13fcfdb6d5SSaksham Jain #define CONFIG_SHA_HW_ACCEL 142ed948f4SAneesh Bansal #define CONFIG_SHA_PROG_HW_ACCEL 152ed948f4SAneesh Bansal 16028ac8c7SSumit Garg #define CONFIG_SPL_BOARD_INIT 17b63f8a43SSimon Glass #ifdef CONFIG_SPL_BUILD 18028ac8c7SSumit Garg /* 19028ac8c7SSumit Garg * Define the key hash for U-Boot here if public/private key pair used to 20028ac8c7SSumit Garg * sign U-boot are different from the SRK hash put in the fuse 21028ac8c7SSumit Garg * Example of defining KEY_HASH is 22028ac8c7SSumit Garg * #define CONFIG_SPL_UBOOT_KEY_HASH \ 23028ac8c7SSumit Garg * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 24028ac8c7SSumit Garg * else leave it defined as NULL 25028ac8c7SSumit Garg */ 26028ac8c7SSumit Garg 27028ac8c7SSumit Garg #define CONFIG_SPL_UBOOT_KEY_HASH NULL 28028ac8c7SSumit Garg #endif /* ifdef CONFIG_SPL_BUILD */ 29028ac8c7SSumit Garg 30*70f9661cSRuchika Gupta #define CONFIG_KEY_REVOCATION 31*70f9661cSRuchika Gupta 32028ac8c7SSumit Garg #ifndef CONFIG_SPL_BUILD 33028ac8c7SSumit Garg #define CONFIG_CMD_BLOB 34028ac8c7SSumit Garg #define CONFIG_CMD_HASH 352ed948f4SAneesh Bansal #ifndef CONFIG_SYS_RAMBOOT 362ed948f4SAneesh Bansal /* The key used for verification of next level images 372ed948f4SAneesh Bansal * is picked up from an Extension Table which has 382ed948f4SAneesh Bansal * been verified by the ISBC (Internal Secure boot Code) 392ed948f4SAneesh Bansal * in boot ROM of the SoC. 402ed948f4SAneesh Bansal * The feature is only applicable in case of NOR boot and is 412ed948f4SAneesh Bansal * not applicable in case of RAMBOOT (NAND, SD, SPI). 42ac55dadbSUdit Agarwal * For LS, this feature is available for all device if IE Table 43ac55dadbSUdit Agarwal * is copied to XIP memory 44ac55dadbSUdit Agarwal * Also, for LS, ISBC doesn't verify this table. 452ed948f4SAneesh Bansal */ 462ed948f4SAneesh Bansal #define CONFIG_FSL_ISBC_KEY_EXT 472ed948f4SAneesh Bansal 48fd6dbc98SSaksham Jain #endif 49fd6dbc98SSaksham Jain 50b3635f57SVinitha Pillai-B57223 #if defined(CONFIG_FSL_LAYERSCAPE) 51b3635f57SVinitha Pillai-B57223 /* 52b3635f57SVinitha Pillai-B57223 * For fsl layerscape based platforms, ESBC image Address in Header 53b3635f57SVinitha Pillai-B57223 * is 64 bit. 54fcfdb6d5SSaksham Jain */ 55ef6c55a2SAneesh Bansal #define CONFIG_ESBC_ADDR_64BIT 56ef6c55a2SAneesh Bansal #endif 57ef6c55a2SAneesh Bansal 583c1d218aSYork Sun #ifdef CONFIG_LS2080A 59bef238cbSSaksham Jain #define CONFIG_EXTRA_ENV \ 60bef238cbSSaksham Jain "setenv fdt_high 0xa0000000;" \ 61bef238cbSSaksham Jain "setenv initrd_high 0xcfffffff;" \ 62bef238cbSSaksham Jain "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 63bef238cbSSaksham Jain #else 6498cb0efdSgaurav rana #define CONFIG_EXTRA_ENV \ 6569d4b48cSSumit Garg "setenv fdt_high 0xffffffff;" \ 6669d4b48cSSumit Garg "setenv initrd_high 0xffffffff;" \ 6798cb0efdSgaurav rana "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 68bef238cbSSaksham Jain #endif 6998cb0efdSgaurav rana 703f701cc5SSaksham Jain /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from 713f701cc5SSaksham Jain * Non-XIP Memory (Nand/SD)*/ 7239199356SUdit Agarwal #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ 7369d4b48cSSumit Garg defined(CONFIG_SD_BOOT) 743f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_COPY_RAM 753f701cc5SSaksham Jain #endif 7669d4b48cSSumit Garg /* The address needs to be modified according to NOR, NAND, SD and 7769d4b48cSSumit Garg * DDR memory map 7869d4b48cSSumit Garg */ 7939199356SUdit Agarwal #ifdef CONFIG_FSL_LSCH3 8039199356SUdit Agarwal #define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 8139199356SUdit Agarwal #define CONFIG_BS_ADDR_DEVICE 0x580e00000 8239199356SUdit Agarwal #define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 8339199356SUdit Agarwal #define CONFIG_BS_ADDR_RAM 0xa0e00000 8469d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00002000 8569d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00001000 86216e93a1SSaksham Jain #else 8769d4b48cSSumit Garg #ifdef CONFIG_SD_BOOT 8869d4b48cSSumit Garg /* For SD boot address and size are assigned in terms of sector 8969d4b48cSSumit Garg * offset and no. of sectors respectively. 9069d4b48cSSumit Garg */ 91*70f9661cSRuchika Gupta #if defined(CONFIG_LS1043A) 92*70f9661cSRuchika Gupta #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920 93*70f9661cSRuchika Gupta #else 949b6639faSVinitha Pillai #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 95*70f9661cSRuchika Gupta #endif 969b6639faSVinitha Pillai #define CONFIG_BS_ADDR_DEVICE 0x00000940 9769d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00000010 9869d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00000008 99b3635f57SVinitha Pillai-B57223 #elif defined(CONFIG_QSPI_BOOT) 100b3635f57SVinitha Pillai-B57223 #ifdef CONFIG_ARCH_LS1046A 101b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000 102b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_ADDR_DEVICE 0x40800000 103d2a99502SVinitha Pillai-B57223 #elif defined(CONFIG_ARCH_LS1012A) 104d2a99502SVinitha Pillai-B57223 #define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000 105d2a99502SVinitha Pillai-B57223 #define CONFIG_BS_ADDR_DEVICE 0x40060000 10669d4b48cSSumit Garg #else 107b3635f57SVinitha Pillai-B57223 #error "Platform not supported" 108b3635f57SVinitha Pillai-B57223 #endif 109b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_HDR_SIZE 0x00002000 110b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_SIZE 0x00001000 111b3635f57SVinitha Pillai-B57223 #else /* Default NOR Boot */ 11269d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 11369d4b48cSSumit Garg #define CONFIG_BS_ADDR_DEVICE 0x60060000 11469d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00002000 11569d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00001000 116b3635f57SVinitha Pillai-B57223 #endif 11769d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_RAM 0x81000000 11869d4b48cSSumit Garg #define CONFIG_BS_ADDR_RAM 0x81020000 1193f701cc5SSaksham Jain #endif 1203f701cc5SSaksham Jain 1213f701cc5SSaksham Jain #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 1223f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 1233f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM 1243f701cc5SSaksham Jain #else 12569d4b48cSSumit Garg #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE 12669d4b48cSSumit Garg /* BOOTSCRIPT_ADDR is not required */ 127216e93a1SSaksham Jain #endif 12898cb0efdSgaurav rana 12907806e62SSumit Garg #ifdef CONFIG_FSL_LS_PPA 13007806e62SSumit Garg /* Define the key hash here if SRK used for signing PPA image is 13107806e62SSumit Garg * different from SRK hash put in SFP used for U-Boot. 13207806e62SSumit Garg * Example 133d1a795acSVinitha Pillai-B57223 * #define PPA_KEY_HASH \ 13407806e62SSumit Garg * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 13507806e62SSumit Garg */ 136d1a795acSVinitha Pillai-B57223 #define PPA_KEY_HASH NULL 13707806e62SSumit Garg #endif /* ifdef CONFIG_FSL_LS_PPA */ 13807806e62SSumit Garg 139bdc22074SAneesh Bansal #include <config_fsl_chain_trust.h> 140028ac8c7SSumit Garg #endif /* #ifndef CONFIG_SPL_BUILD */ 141bdc22074SAneesh Bansal #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 14298cb0efdSgaurav rana #endif 143