xref: /rk3399_rockchip-uboot/arch/arm/include/asm/fsl_secure_boot.h (revision 39199356e9ff3db2cd7851a0e29840f1972fb959)
198cb0efdSgaurav rana /*
298cb0efdSgaurav rana  * Copyright 2015 Freescale Semiconductor, Inc.
398cb0efdSgaurav rana  *
498cb0efdSgaurav rana  * SPDX-License-Identifier:	GPL-2.0+
598cb0efdSgaurav rana  */
698cb0efdSgaurav rana 
798cb0efdSgaurav rana #ifndef __FSL_SECURE_BOOT_H
898cb0efdSgaurav rana #define __FSL_SECURE_BOOT_H
998cb0efdSgaurav rana 
1098cb0efdSgaurav rana #ifdef CONFIG_SECURE_BOOT
11bdc22074SAneesh Bansal 
12bdc22074SAneesh Bansal #ifndef CONFIG_FIT_SIGNATURE
13bdc22074SAneesh Bansal #define CONFIG_CHAIN_OF_TRUST
14bdc22074SAneesh Bansal #endif
15bdc22074SAneesh Bansal 
16bdc22074SAneesh Bansal #endif
17bdc22074SAneesh Bansal 
18bdc22074SAneesh Bansal #ifdef CONFIG_CHAIN_OF_TRUST
192ed948f4SAneesh Bansal #define CONFIG_CMD_ESBC_VALIDATE
202ed948f4SAneesh Bansal #define CONFIG_FSL_SEC_MON
21fcfdb6d5SSaksham Jain #define CONFIG_SHA_HW_ACCEL
222ed948f4SAneesh Bansal #define CONFIG_SHA_PROG_HW_ACCEL
232ed948f4SAneesh Bansal #define CONFIG_RSA_FREESCALE_EXP
249711f528SAneesh Bansal 
252ed948f4SAneesh Bansal #ifndef CONFIG_FSL_CAAM
262ed948f4SAneesh Bansal #define CONFIG_FSL_CAAM
272ed948f4SAneesh Bansal #endif
282ed948f4SAneesh Bansal 
29028ac8c7SSumit Garg #define CONFIG_SPL_BOARD_INIT
30b63f8a43SSimon Glass #ifdef CONFIG_SPL_BUILD
31028ac8c7SSumit Garg /*
32028ac8c7SSumit Garg  * Define the key hash for U-Boot here if public/private key pair used to
33028ac8c7SSumit Garg  * sign U-boot are different from the SRK hash put in the fuse
34028ac8c7SSumit Garg  * Example of defining KEY_HASH is
35028ac8c7SSumit Garg  * #define CONFIG_SPL_UBOOT_KEY_HASH \
36028ac8c7SSumit Garg  *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
37028ac8c7SSumit Garg  * else leave it defined as NULL
38028ac8c7SSumit Garg  */
39028ac8c7SSumit Garg 
40028ac8c7SSumit Garg #define CONFIG_SPL_UBOOT_KEY_HASH	NULL
41028ac8c7SSumit Garg #endif /* ifdef CONFIG_SPL_BUILD */
42028ac8c7SSumit Garg 
43028ac8c7SSumit Garg #ifndef CONFIG_SPL_BUILD
44028ac8c7SSumit Garg #define CONFIG_CMD_BLOB
45028ac8c7SSumit Garg #define CONFIG_CMD_HASH
462ed948f4SAneesh Bansal #define CONFIG_KEY_REVOCATION
472ed948f4SAneesh Bansal #ifndef CONFIG_SYS_RAMBOOT
482ed948f4SAneesh Bansal /* The key used for verification of next level images
492ed948f4SAneesh Bansal  * is picked up from an Extension Table which has
502ed948f4SAneesh Bansal  * been verified by the ISBC (Internal Secure boot Code)
512ed948f4SAneesh Bansal  * in boot ROM of the SoC.
522ed948f4SAneesh Bansal  * The feature is only applicable in case of NOR boot and is
532ed948f4SAneesh Bansal  * not applicable in case of RAMBOOT (NAND, SD, SPI).
542ed948f4SAneesh Bansal  */
55fd6dbc98SSaksham Jain #ifndef CONFIG_ESBC_HDR_LS
56fd6dbc98SSaksham Jain /* Current Key EXT feature not available in LS ESBC Header */
572ed948f4SAneesh Bansal #define CONFIG_FSL_ISBC_KEY_EXT
582ed948f4SAneesh Bansal #endif
592ed948f4SAneesh Bansal 
60fd6dbc98SSaksham Jain #endif
61fd6dbc98SSaksham Jain 
623c1d218aSYork Sun #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
63fcfdb6d5SSaksham Jain /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
643c1d218aSYork Sun  * Similiarly for LS2080
65fcfdb6d5SSaksham Jain  */
66ef6c55a2SAneesh Bansal #define CONFIG_ESBC_ADDR_64BIT
67ef6c55a2SAneesh Bansal #endif
68ef6c55a2SAneesh Bansal 
693c1d218aSYork Sun #ifdef CONFIG_LS2080A
70bef238cbSSaksham Jain #define CONFIG_EXTRA_ENV \
71bef238cbSSaksham Jain 	"setenv fdt_high 0xa0000000;"	\
72bef238cbSSaksham Jain 	"setenv initrd_high 0xcfffffff;"	\
73bef238cbSSaksham Jain 	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
74bef238cbSSaksham Jain #else
7598cb0efdSgaurav rana #define CONFIG_EXTRA_ENV \
7669d4b48cSSumit Garg 	"setenv fdt_high 0xffffffff;"	\
7769d4b48cSSumit Garg 	"setenv initrd_high 0xffffffff;"	\
7898cb0efdSgaurav rana 	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
79bef238cbSSaksham Jain #endif
8098cb0efdSgaurav rana 
813f701cc5SSaksham Jain /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
823f701cc5SSaksham Jain  * Non-XIP Memory (Nand/SD)*/
83*39199356SUdit Agarwal #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
8469d4b48cSSumit Garg 	defined(CONFIG_SD_BOOT)
853f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_COPY_RAM
863f701cc5SSaksham Jain #endif
8769d4b48cSSumit Garg /* The address needs to be modified according to NOR, NAND, SD and
8869d4b48cSSumit Garg  * DDR memory map
8969d4b48cSSumit Garg  */
90*39199356SUdit Agarwal #ifdef CONFIG_FSL_LSCH3
91*39199356SUdit Agarwal #define CONFIG_BS_HDR_ADDR_DEVICE	0x580d00000
92*39199356SUdit Agarwal #define CONFIG_BS_ADDR_DEVICE		0x580e00000
93*39199356SUdit Agarwal #define CONFIG_BS_HDR_ADDR_RAM		0xa0d00000
94*39199356SUdit Agarwal #define CONFIG_BS_ADDR_RAM		0xa0e00000
9569d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE		0x00002000
9669d4b48cSSumit Garg #define CONFIG_BS_SIZE			0x00001000
97216e93a1SSaksham Jain #else
9869d4b48cSSumit Garg #ifdef CONFIG_SD_BOOT
9969d4b48cSSumit Garg /* For SD boot address and size are assigned in terms of sector
10069d4b48cSSumit Garg  * offset and no. of sectors respectively.
10169d4b48cSSumit Garg  */
10269d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_DEVICE	0x00000800
10369d4b48cSSumit Garg #define CONFIG_BS_ADDR_DEVICE		0x00000840
10469d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE		0x00000010
10569d4b48cSSumit Garg #define CONFIG_BS_SIZE			0x00000008
10669d4b48cSSumit Garg #else
10769d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_DEVICE	0x600a0000
10869d4b48cSSumit Garg #define CONFIG_BS_ADDR_DEVICE		0x60060000
10969d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE		0x00002000
11069d4b48cSSumit Garg #define CONFIG_BS_SIZE			0x00001000
11169d4b48cSSumit Garg #endif /* #ifdef CONFIG_SD_BOOT */
11269d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_RAM		0x81000000
11369d4b48cSSumit Garg #define CONFIG_BS_ADDR_RAM		0x81020000
1143f701cc5SSaksham Jain #endif
1153f701cc5SSaksham Jain 
1163f701cc5SSaksham Jain #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
1173f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
1183f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_ADDR		CONFIG_BS_ADDR_RAM
1193f701cc5SSaksham Jain #else
12069d4b48cSSumit Garg #define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_DEVICE
12169d4b48cSSumit Garg /* BOOTSCRIPT_ADDR is not required */
122216e93a1SSaksham Jain #endif
12398cb0efdSgaurav rana 
12407806e62SSumit Garg #ifdef CONFIG_FSL_LS_PPA
12507806e62SSumit Garg #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
12607806e62SSumit Garg #ifdef CONFIG_LS1043A
12707806e62SSumit Garg #define CONFIG_SYS_LS_PPA_ESBC_ADDR	0x600c0000
12807806e62SSumit Garg #endif
12907806e62SSumit Garg #else
13007806e62SSumit Garg #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
13107806e62SSumit Garg #endif /* ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP */
13207806e62SSumit Garg 
13307806e62SSumit Garg /* Define the key hash here if SRK used for signing PPA image is
13407806e62SSumit Garg  * different from SRK hash put in SFP used for U-Boot.
13507806e62SSumit Garg  * Example
13607806e62SSumit Garg  * #define CONFIG_PPA_KEY_HASH \
13707806e62SSumit Garg  *	"41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
13807806e62SSumit Garg  */
13907806e62SSumit Garg #define CONFIG_PPA_KEY_HASH		NULL
14007806e62SSumit Garg #endif /* ifdef CONFIG_FSL_LS_PPA */
14107806e62SSumit Garg 
142bdc22074SAneesh Bansal #include <config_fsl_chain_trust.h>
143028ac8c7SSumit Garg #endif /* #ifndef CONFIG_SPL_BUILD */
144bdc22074SAneesh Bansal #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
14598cb0efdSgaurav rana #endif
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