198cb0efdSgaurav rana /* 298cb0efdSgaurav rana * Copyright 2015 Freescale Semiconductor, Inc. 398cb0efdSgaurav rana * 498cb0efdSgaurav rana * SPDX-License-Identifier: GPL-2.0+ 598cb0efdSgaurav rana */ 698cb0efdSgaurav rana 798cb0efdSgaurav rana #ifndef __FSL_SECURE_BOOT_H 898cb0efdSgaurav rana #define __FSL_SECURE_BOOT_H 998cb0efdSgaurav rana 1098cb0efdSgaurav rana #ifdef CONFIG_SECURE_BOOT 11bdc22074SAneesh Bansal 12bdc22074SAneesh Bansal #ifndef CONFIG_FIT_SIGNATURE 13bdc22074SAneesh Bansal #define CONFIG_CHAIN_OF_TRUST 14bdc22074SAneesh Bansal #endif 15bdc22074SAneesh Bansal 16bdc22074SAneesh Bansal #endif 17bdc22074SAneesh Bansal 18bdc22074SAneesh Bansal #ifdef CONFIG_CHAIN_OF_TRUST 192ed948f4SAneesh Bansal #define CONFIG_CMD_ESBC_VALIDATE 202ed948f4SAneesh Bansal #define CONFIG_FSL_SEC_MON 21fcfdb6d5SSaksham Jain #define CONFIG_SHA_HW_ACCEL 222ed948f4SAneesh Bansal #define CONFIG_SHA_PROG_HW_ACCEL 232ed948f4SAneesh Bansal #define CONFIG_RSA_FREESCALE_EXP 249711f528SAneesh Bansal 252ed948f4SAneesh Bansal #ifndef CONFIG_FSL_CAAM 262ed948f4SAneesh Bansal #define CONFIG_FSL_CAAM 272ed948f4SAneesh Bansal #endif 282ed948f4SAneesh Bansal 29*028ac8c7SSumit Garg #ifdef CONFIG_SPL_BUILD 30*028ac8c7SSumit Garg #define CONFIG_SPL_BOARD_INIT 31*028ac8c7SSumit Garg #define CONFIG_SPL_DM 1 32*028ac8c7SSumit Garg #define CONFIG_SPL_CRYPTO_SUPPORT 33*028ac8c7SSumit Garg #define CONFIG_SPL_HASH_SUPPORT 34*028ac8c7SSumit Garg #define CONFIG_SPL_RSA 35*028ac8c7SSumit Garg #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 36*028ac8c7SSumit Garg /* 37*028ac8c7SSumit Garg * Define the key hash for U-Boot here if public/private key pair used to 38*028ac8c7SSumit Garg * sign U-boot are different from the SRK hash put in the fuse 39*028ac8c7SSumit Garg * Example of defining KEY_HASH is 40*028ac8c7SSumit Garg * #define CONFIG_SPL_UBOOT_KEY_HASH \ 41*028ac8c7SSumit Garg * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 42*028ac8c7SSumit Garg * else leave it defined as NULL 43*028ac8c7SSumit Garg */ 44*028ac8c7SSumit Garg 45*028ac8c7SSumit Garg #define CONFIG_SPL_UBOOT_KEY_HASH NULL 46*028ac8c7SSumit Garg #endif /* ifdef CONFIG_SPL_BUILD */ 47*028ac8c7SSumit Garg 48*028ac8c7SSumit Garg #ifndef CONFIG_SPL_BUILD 49*028ac8c7SSumit Garg #define CONFIG_CMD_BLOB 50*028ac8c7SSumit Garg #define CONFIG_CMD_HASH 512ed948f4SAneesh Bansal #define CONFIG_KEY_REVOCATION 522ed948f4SAneesh Bansal #ifndef CONFIG_SYS_RAMBOOT 532ed948f4SAneesh Bansal /* The key used for verification of next level images 542ed948f4SAneesh Bansal * is picked up from an Extension Table which has 552ed948f4SAneesh Bansal * been verified by the ISBC (Internal Secure boot Code) 562ed948f4SAneesh Bansal * in boot ROM of the SoC. 572ed948f4SAneesh Bansal * The feature is only applicable in case of NOR boot and is 582ed948f4SAneesh Bansal * not applicable in case of RAMBOOT (NAND, SD, SPI). 592ed948f4SAneesh Bansal */ 60fd6dbc98SSaksham Jain #ifndef CONFIG_ESBC_HDR_LS 61fd6dbc98SSaksham Jain /* Current Key EXT feature not available in LS ESBC Header */ 622ed948f4SAneesh Bansal #define CONFIG_FSL_ISBC_KEY_EXT 632ed948f4SAneesh Bansal #endif 642ed948f4SAneesh Bansal 65fd6dbc98SSaksham Jain #endif 66fd6dbc98SSaksham Jain 673c1d218aSYork Sun #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) 68fcfdb6d5SSaksham Jain /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit 693c1d218aSYork Sun * Similiarly for LS2080 70fcfdb6d5SSaksham Jain */ 71ef6c55a2SAneesh Bansal #define CONFIG_ESBC_ADDR_64BIT 72ef6c55a2SAneesh Bansal #endif 73ef6c55a2SAneesh Bansal 743c1d218aSYork Sun #ifdef CONFIG_LS2080A 75bef238cbSSaksham Jain #define CONFIG_EXTRA_ENV \ 76bef238cbSSaksham Jain "setenv fdt_high 0xa0000000;" \ 77bef238cbSSaksham Jain "setenv initrd_high 0xcfffffff;" \ 78bef238cbSSaksham Jain "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 79bef238cbSSaksham Jain #else 8098cb0efdSgaurav rana #define CONFIG_EXTRA_ENV \ 8198cb0efdSgaurav rana "setenv fdt_high 0xcfffffff;" \ 8298cb0efdSgaurav rana "setenv initrd_high 0xcfffffff;" \ 8398cb0efdSgaurav rana "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 84bef238cbSSaksham Jain #endif 8598cb0efdSgaurav rana 863f701cc5SSaksham Jain /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from 873f701cc5SSaksham Jain * Non-XIP Memory (Nand/SD)*/ 883c1d218aSYork Sun #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) 893f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_COPY_RAM 903f701cc5SSaksham Jain #endif 913f701cc5SSaksham Jain /* The address needs to be modified according to NOR and DDR memory map */ 923c1d218aSYork Sun #ifdef CONFIG_LS2080A 933f701cc5SSaksham Jain #define CONFIG_BS_HDR_ADDR_FLASH 0x583920000 943f701cc5SSaksham Jain #define CONFIG_BS_ADDR_FLASH 0x583900000 953f701cc5SSaksham Jain #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 963f701cc5SSaksham Jain #define CONFIG_BS_ADDR_RAM 0xa3900000 97216e93a1SSaksham Jain #else 983f701cc5SSaksham Jain #define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000 993f701cc5SSaksham Jain #define CONFIG_BS_ADDR_FLASH 0x60060000 1003f701cc5SSaksham Jain #define CONFIG_BS_HDR_ADDR_RAM 0xa0060000 1013f701cc5SSaksham Jain #define CONFIG_BS_ADDR_RAM 0xa0060000 1023f701cc5SSaksham Jain #endif 1033f701cc5SSaksham Jain 1043f701cc5SSaksham Jain #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 1053f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 1063f701cc5SSaksham Jain #define CONFIG_BS_HDR_SIZE 0x00002000 1073f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM 1083f701cc5SSaksham Jain #define CONFIG_BS_SIZE 0x00001000 1093f701cc5SSaksham Jain #else 1103f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH 1113f701cc5SSaksham Jain /* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */ 112216e93a1SSaksham Jain #endif 11398cb0efdSgaurav rana 114bdc22074SAneesh Bansal #include <config_fsl_chain_trust.h> 115*028ac8c7SSumit Garg #endif /* #ifndef CONFIG_SPL_BUILD */ 116bdc22074SAneesh Bansal #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 11798cb0efdSgaurav rana #endif 118