198cb0efdSgaurav rana /* 298cb0efdSgaurav rana * Copyright 2015 Freescale Semiconductor, Inc. 398cb0efdSgaurav rana * 498cb0efdSgaurav rana * SPDX-License-Identifier: GPL-2.0+ 598cb0efdSgaurav rana */ 698cb0efdSgaurav rana 798cb0efdSgaurav rana #ifndef __FSL_SECURE_BOOT_H 898cb0efdSgaurav rana #define __FSL_SECURE_BOOT_H 998cb0efdSgaurav rana 10bdc22074SAneesh Bansal #ifdef CONFIG_CHAIN_OF_TRUST 112ed948f4SAneesh Bansal #define CONFIG_FSL_SEC_MON 122ed948f4SAneesh Bansal 13b63f8a43SSimon Glass #ifdef CONFIG_SPL_BUILD 14028ac8c7SSumit Garg /* 15028ac8c7SSumit Garg * Define the key hash for U-Boot here if public/private key pair used to 16028ac8c7SSumit Garg * sign U-boot are different from the SRK hash put in the fuse 17028ac8c7SSumit Garg * Example of defining KEY_HASH is 18028ac8c7SSumit Garg * #define CONFIG_SPL_UBOOT_KEY_HASH \ 19028ac8c7SSumit Garg * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 20028ac8c7SSumit Garg * else leave it defined as NULL 21028ac8c7SSumit Garg */ 22028ac8c7SSumit Garg 23028ac8c7SSumit Garg #define CONFIG_SPL_UBOOT_KEY_HASH NULL 24028ac8c7SSumit Garg #endif /* ifdef CONFIG_SPL_BUILD */ 25028ac8c7SSumit Garg 2670f9661cSRuchika Gupta #define CONFIG_KEY_REVOCATION 2770f9661cSRuchika Gupta 28028ac8c7SSumit Garg #ifndef CONFIG_SPL_BUILD 292ed948f4SAneesh Bansal #ifndef CONFIG_SYS_RAMBOOT 302ed948f4SAneesh Bansal /* The key used for verification of next level images 312ed948f4SAneesh Bansal * is picked up from an Extension Table which has 322ed948f4SAneesh Bansal * been verified by the ISBC (Internal Secure boot Code) 332ed948f4SAneesh Bansal * in boot ROM of the SoC. 342ed948f4SAneesh Bansal * The feature is only applicable in case of NOR boot and is 352ed948f4SAneesh Bansal * not applicable in case of RAMBOOT (NAND, SD, SPI). 36ac55dadbSUdit Agarwal * For LS, this feature is available for all device if IE Table 37ac55dadbSUdit Agarwal * is copied to XIP memory 38ac55dadbSUdit Agarwal * Also, for LS, ISBC doesn't verify this table. 392ed948f4SAneesh Bansal */ 402ed948f4SAneesh Bansal #define CONFIG_FSL_ISBC_KEY_EXT 412ed948f4SAneesh Bansal 42fd6dbc98SSaksham Jain #endif 43fd6dbc98SSaksham Jain 44b3635f57SVinitha Pillai-B57223 #if defined(CONFIG_FSL_LAYERSCAPE) 45b3635f57SVinitha Pillai-B57223 /* 46b3635f57SVinitha Pillai-B57223 * For fsl layerscape based platforms, ESBC image Address in Header 47b3635f57SVinitha Pillai-B57223 * is 64 bit. 48fcfdb6d5SSaksham Jain */ 49ef6c55a2SAneesh Bansal #define CONFIG_ESBC_ADDR_64BIT 50ef6c55a2SAneesh Bansal #endif 51ef6c55a2SAneesh Bansal 524a3ab193SYork Sun #ifdef CONFIG_ARCH_LS2080A 53bef238cbSSaksham Jain #define CONFIG_EXTRA_ENV \ 54bef238cbSSaksham Jain "setenv fdt_high 0xa0000000;" \ 55bef238cbSSaksham Jain "setenv initrd_high 0xcfffffff;" \ 56bef238cbSSaksham Jain "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 57bef238cbSSaksham Jain #else 5898cb0efdSgaurav rana #define CONFIG_EXTRA_ENV \ 5969d4b48cSSumit Garg "setenv fdt_high 0xffffffff;" \ 6069d4b48cSSumit Garg "setenv initrd_high 0xffffffff;" \ 6198cb0efdSgaurav rana "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 62bef238cbSSaksham Jain #endif 6398cb0efdSgaurav rana 643f701cc5SSaksham Jain /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from 653f701cc5SSaksham Jain * Non-XIP Memory (Nand/SD)*/ 6639199356SUdit Agarwal #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ 67762f92a6SRuchika Gupta defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) 683f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_COPY_RAM 693f701cc5SSaksham Jain #endif 7069d4b48cSSumit Garg /* The address needs to be modified according to NOR, NAND, SD and 7169d4b48cSSumit Garg * DDR memory map 7269d4b48cSSumit Garg */ 7339199356SUdit Agarwal #ifdef CONFIG_FSL_LSCH3 7439199356SUdit Agarwal #define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 7539199356SUdit Agarwal #define CONFIG_BS_ADDR_DEVICE 0x580e00000 7639199356SUdit Agarwal #define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 7739199356SUdit Agarwal #define CONFIG_BS_ADDR_RAM 0xa0e00000 7869d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00002000 7969d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00001000 80216e93a1SSaksham Jain #else 8169d4b48cSSumit Garg #ifdef CONFIG_SD_BOOT 8269d4b48cSSumit Garg /* For SD boot address and size are assigned in terms of sector 8369d4b48cSSumit Garg * offset and no. of sectors respectively. 8469d4b48cSSumit Garg */ 85*c1303bfdSYork Sun #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 8670f9661cSRuchika Gupta #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920 8770f9661cSRuchika Gupta #else 889b6639faSVinitha Pillai #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 8970f9661cSRuchika Gupta #endif 909b6639faSVinitha Pillai #define CONFIG_BS_ADDR_DEVICE 0x00000940 9169d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00000010 9269d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00000008 93762f92a6SRuchika Gupta #elif defined(CONFIG_NAND_BOOT) 94762f92a6SRuchika Gupta #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 95762f92a6SRuchika Gupta #define CONFIG_BS_ADDR_DEVICE 0x00802000 96762f92a6SRuchika Gupta #define CONFIG_BS_HDR_SIZE 0x00002000 97762f92a6SRuchika Gupta #define CONFIG_BS_SIZE 0x00001000 98b3635f57SVinitha Pillai-B57223 #elif defined(CONFIG_QSPI_BOOT) 99b3635f57SVinitha Pillai-B57223 #ifdef CONFIG_ARCH_LS1046A 100b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000 101b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_ADDR_DEVICE 0x40800000 102d2a99502SVinitha Pillai-B57223 #elif defined(CONFIG_ARCH_LS1012A) 103d2a99502SVinitha Pillai-B57223 #define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000 104d2a99502SVinitha Pillai-B57223 #define CONFIG_BS_ADDR_DEVICE 0x40060000 10569d4b48cSSumit Garg #else 106b3635f57SVinitha Pillai-B57223 #error "Platform not supported" 107b3635f57SVinitha Pillai-B57223 #endif 108b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_HDR_SIZE 0x00002000 109b3635f57SVinitha Pillai-B57223 #define CONFIG_BS_SIZE 0x00001000 110b3635f57SVinitha Pillai-B57223 #else /* Default NOR Boot */ 11169d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 11269d4b48cSSumit Garg #define CONFIG_BS_ADDR_DEVICE 0x60060000 11369d4b48cSSumit Garg #define CONFIG_BS_HDR_SIZE 0x00002000 11469d4b48cSSumit Garg #define CONFIG_BS_SIZE 0x00001000 115b3635f57SVinitha Pillai-B57223 #endif 11669d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_RAM 0x81000000 11769d4b48cSSumit Garg #define CONFIG_BS_ADDR_RAM 0x81020000 1183f701cc5SSaksham Jain #endif 1193f701cc5SSaksham Jain 1203f701cc5SSaksham Jain #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 1213f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 1223f701cc5SSaksham Jain #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM 1233f701cc5SSaksham Jain #else 12469d4b48cSSumit Garg #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE 12569d4b48cSSumit Garg /* BOOTSCRIPT_ADDR is not required */ 126216e93a1SSaksham Jain #endif 12798cb0efdSgaurav rana 12807806e62SSumit Garg #ifdef CONFIG_FSL_LS_PPA 12907806e62SSumit Garg /* Define the key hash here if SRK used for signing PPA image is 13007806e62SSumit Garg * different from SRK hash put in SFP used for U-Boot. 13107806e62SSumit Garg * Example 132d1a795acSVinitha Pillai-B57223 * #define PPA_KEY_HASH \ 13307806e62SSumit Garg * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 13407806e62SSumit Garg */ 135d1a795acSVinitha Pillai-B57223 #define PPA_KEY_HASH NULL 13607806e62SSumit Garg #endif /* ifdef CONFIG_FSL_LS_PPA */ 13707806e62SSumit Garg 138bdc22074SAneesh Bansal #include <config_fsl_chain_trust.h> 139028ac8c7SSumit Garg #endif /* #ifndef CONFIG_SPL_BUILD */ 140bdc22074SAneesh Bansal #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 14198cb0efdSgaurav rana #endif 142