1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2009 3819833afSPeter Tyser * Marvell Semiconductor <www.marvell.com> 4819833afSPeter Tyser * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5819833afSPeter Tyser * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7819833afSPeter Tyser */ 8819833afSPeter Tyser 9819833afSPeter Tyser #ifndef _ASM_CACHE_H 10819833afSPeter Tyser #define _ASM_CACHE_H 11819833afSPeter Tyser 12819833afSPeter Tyser #include <asm/system.h> 13819833afSPeter Tyser 140ae76531SDavid Feng #ifndef CONFIG_ARM64 150ae76531SDavid Feng 16819833afSPeter Tyser /* 17819833afSPeter Tyser * Invalidate L2 Cache using co-proc instruction 18819833afSPeter Tyser */ 19819833afSPeter Tyser static inline void invalidate_l2_cache(void) 20819833afSPeter Tyser { 21819833afSPeter Tyser unsigned int val=0; 22819833afSPeter Tyser 23819833afSPeter Tyser asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 24819833afSPeter Tyser : : "r" (val) : "cc"); 25819833afSPeter Tyser isb(); 26819833afSPeter Tyser } 27819833afSPeter Tyser 28819833afSPeter Tyser void l2_cache_enable(void); 29819833afSPeter Tyser void l2_cache_disable(void); 30dfa41387SVincent Stehlé void set_section_dcache(int section, enum dcache_option option); 31819833afSPeter Tyser 32*fcfddfd5SJeroen Hofstee void arm_init_before_mmu(void); 33*fcfddfd5SJeroen Hofstee void arm_init_domains(void); 34*fcfddfd5SJeroen Hofstee void cpu_cache_initialization(void); 3596fdbec2SR Sricharan void dram_bank_mmu_setup(int bank); 360ae76531SDavid Feng 370ae76531SDavid Feng #endif 380ae76531SDavid Feng 3944d6cbb6SAnton Staaf /* 4044d6cbb6SAnton Staaf * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We 4144d6cbb6SAnton Staaf * use that value for aligning DMA buffers unless the board config has specified 4244d6cbb6SAnton Staaf * an alternate cache line size. 4344d6cbb6SAnton Staaf */ 4444d6cbb6SAnton Staaf #ifdef CONFIG_SYS_CACHELINE_SIZE 4544d6cbb6SAnton Staaf #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 4644d6cbb6SAnton Staaf #else 4744d6cbb6SAnton Staaf #define ARCH_DMA_MINALIGN 64 4844d6cbb6SAnton Staaf #endif 4944d6cbb6SAnton Staaf 50819833afSPeter Tyser #endif /* _ASM_CACHE_H */ 51