1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2009 3819833afSPeter Tyser * Marvell Semiconductor <www.marvell.com> 4819833afSPeter Tyser * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5819833afSPeter Tyser * 6819833afSPeter Tyser * See file CREDITS for list of people who contributed to this 7819833afSPeter Tyser * project. 8819833afSPeter Tyser * 9819833afSPeter Tyser * This program is free software; you can redistribute it and/or 10819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 11819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 12819833afSPeter Tyser * the License, or (at your option) any later version. 13819833afSPeter Tyser * 14819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 15819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 16819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17819833afSPeter Tyser * GNU General Public License for more details. 18819833afSPeter Tyser * 19819833afSPeter Tyser * You should have received a copy of the GNU General Public License 20819833afSPeter Tyser * along with this program; if not, write to the Free Software 21819833afSPeter Tyser * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22819833afSPeter Tyser * MA 02110-1301 USA 23819833afSPeter Tyser */ 24819833afSPeter Tyser 25819833afSPeter Tyser #ifndef _ASM_CACHE_H 26819833afSPeter Tyser #define _ASM_CACHE_H 27819833afSPeter Tyser 28819833afSPeter Tyser #include <asm/system.h> 29819833afSPeter Tyser 30819833afSPeter Tyser /* 31819833afSPeter Tyser * Invalidate L2 Cache using co-proc instruction 32819833afSPeter Tyser */ 33819833afSPeter Tyser static inline void invalidate_l2_cache(void) 34819833afSPeter Tyser { 35819833afSPeter Tyser unsigned int val=0; 36819833afSPeter Tyser 37819833afSPeter Tyser asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 38819833afSPeter Tyser : : "r" (val) : "cc"); 39819833afSPeter Tyser isb(); 40819833afSPeter Tyser } 41819833afSPeter Tyser 42819833afSPeter Tyser void l2_cache_enable(void); 43819833afSPeter Tyser void l2_cache_disable(void); 44*dfa41387SVincent Stehlé void set_section_dcache(int section, enum dcache_option option); 45819833afSPeter Tyser 4644d6cbb6SAnton Staaf /* 4744d6cbb6SAnton Staaf * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We 4844d6cbb6SAnton Staaf * use that value for aligning DMA buffers unless the board config has specified 4944d6cbb6SAnton Staaf * an alternate cache line size. 5044d6cbb6SAnton Staaf */ 5144d6cbb6SAnton Staaf #ifdef CONFIG_SYS_CACHELINE_SIZE 5244d6cbb6SAnton Staaf #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 5344d6cbb6SAnton Staaf #else 5444d6cbb6SAnton Staaf #define ARCH_DMA_MINALIGN 64 5544d6cbb6SAnton Staaf #endif 5644d6cbb6SAnton Staaf 57819833afSPeter Tyser #endif /* _ASM_CACHE_H */ 58