1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2009 3819833afSPeter Tyser * Marvell Semiconductor <www.marvell.com> 4819833afSPeter Tyser * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5819833afSPeter Tyser * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7819833afSPeter Tyser */ 8819833afSPeter Tyser 9819833afSPeter Tyser #ifndef _ASM_CACHE_H 10819833afSPeter Tyser #define _ASM_CACHE_H 11819833afSPeter Tyser 12819833afSPeter Tyser #include <asm/system.h> 13819833afSPeter Tyser 140ae76531SDavid Feng #ifndef CONFIG_ARM64 150ae76531SDavid Feng 16819833afSPeter Tyser /* 17819833afSPeter Tyser * Invalidate L2 Cache using co-proc instruction 18819833afSPeter Tyser */ 19*3a649407STom Rini #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) 2062e92077SAlbert ARIBAUD void invalidate_l2_cache(void); 2162e92077SAlbert ARIBAUD #else invalidate_l2_cache(void)22819833afSPeter Tyserstatic inline void invalidate_l2_cache(void) 23819833afSPeter Tyser { 24819833afSPeter Tyser unsigned int val=0; 25819833afSPeter Tyser 26819833afSPeter Tyser asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 27819833afSPeter Tyser : : "r" (val) : "cc"); 28819833afSPeter Tyser isb(); 29819833afSPeter Tyser } 3062e92077SAlbert ARIBAUD #endif 31819833afSPeter Tyser 32397b5697SSimon Glass int check_cache_range(unsigned long start, unsigned long stop); 33397b5697SSimon Glass 34819833afSPeter Tyser void l2_cache_enable(void); 35819833afSPeter Tyser void l2_cache_disable(void); 36dfa41387SVincent Stehlé void set_section_dcache(int section, enum dcache_option option); 37819833afSPeter Tyser 38fcfddfd5SJeroen Hofstee void arm_init_before_mmu(void); 39fcfddfd5SJeroen Hofstee void arm_init_domains(void); 40fcfddfd5SJeroen Hofstee void cpu_cache_initialization(void); 4196fdbec2SR Sricharan void dram_bank_mmu_setup(int bank); 420ae76531SDavid Feng 430ae76531SDavid Feng #endif 440ae76531SDavid Feng 4544d6cbb6SAnton Staaf /* 46067716baSTom Rini * The value of the largest data cache relevant to DMA operations shall be set 47067716baSTom Rini * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger 48067716baSTom Rini * value than found in the L1 cache but this is OK to use in terms of 49067716baSTom Rini * alignment. 5044d6cbb6SAnton Staaf */ 5144d6cbb6SAnton Staaf #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 5244d6cbb6SAnton Staaf 53819833afSPeter Tyser #endif /* _ASM_CACHE_H */ 54