1*96b61ab1SVikas Manocha /* 2*96b61ab1SVikas Manocha * (C) Copyright 2017 3*96b61ab1SVikas Manocha * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*96b61ab1SVikas Manocha * 5*96b61ab1SVikas Manocha * SPDX-License-Identifier: GPL-2.0+ 6*96b61ab1SVikas Manocha */ 7*96b61ab1SVikas Manocha 8*96b61ab1SVikas Manocha enum region_number { 9*96b61ab1SVikas Manocha REGION_0 = 0, 10*96b61ab1SVikas Manocha REGION_1, 11*96b61ab1SVikas Manocha REGION_2, 12*96b61ab1SVikas Manocha REGION_3, 13*96b61ab1SVikas Manocha REGION_4, 14*96b61ab1SVikas Manocha REGION_5, 15*96b61ab1SVikas Manocha REGION_6, 16*96b61ab1SVikas Manocha REGION_7, 17*96b61ab1SVikas Manocha }; 18*96b61ab1SVikas Manocha 19*96b61ab1SVikas Manocha enum ap { 20*96b61ab1SVikas Manocha NO_ACCESS = 0, 21*96b61ab1SVikas Manocha PRIV_RW_USR_NO, 22*96b61ab1SVikas Manocha PRIV_RW_USR_RO, 23*96b61ab1SVikas Manocha PRIV_RW_USR_RW, 24*96b61ab1SVikas Manocha UNPREDICTABLE, 25*96b61ab1SVikas Manocha PRIV_RO_USR_NO, 26*96b61ab1SVikas Manocha PRIV_RO_USR_RO, 27*96b61ab1SVikas Manocha }; 28*96b61ab1SVikas Manocha 29*96b61ab1SVikas Manocha enum mr_attr { 30*96b61ab1SVikas Manocha STRONG_ORDER = 0, 31*96b61ab1SVikas Manocha SHARED_WRITE_BUFFERED, 32*96b61ab1SVikas Manocha O_I_WT_NO_WR_ALLOC, 33*96b61ab1SVikas Manocha O_I_WB_NO_WR_ALLOC, 34*96b61ab1SVikas Manocha O_I_NON_CACHEABLE, 35*96b61ab1SVikas Manocha O_I_WB_RD_WR_ALLOC, 36*96b61ab1SVikas Manocha DEVICE_NON_SHARED, 37*96b61ab1SVikas Manocha }; 38*96b61ab1SVikas Manocha enum size { 39*96b61ab1SVikas Manocha REGION_8MB = 22, 40*96b61ab1SVikas Manocha REGION_16MB, 41*96b61ab1SVikas Manocha REGION_32MB, 42*96b61ab1SVikas Manocha REGION_64MB, 43*96b61ab1SVikas Manocha REGION_128MB, 44*96b61ab1SVikas Manocha REGION_256MB, 45*96b61ab1SVikas Manocha REGION_512MB, 46*96b61ab1SVikas Manocha REGION_1GB, 47*96b61ab1SVikas Manocha REGION_2GB, 48*96b61ab1SVikas Manocha REGION_4GB, 49*96b61ab1SVikas Manocha }; 50*96b61ab1SVikas Manocha 51*96b61ab1SVikas Manocha enum xn { 52*96b61ab1SVikas Manocha XN_DIS = 0, 53*96b61ab1SVikas Manocha XN_EN, 54*96b61ab1SVikas Manocha }; 55*96b61ab1SVikas Manocha 56*96b61ab1SVikas Manocha struct mpu_region_config { 57*96b61ab1SVikas Manocha uint32_t start_addr; 58*96b61ab1SVikas Manocha enum region_number region_no; 59*96b61ab1SVikas Manocha enum xn xn; 60*96b61ab1SVikas Manocha enum ap ap; 61*96b61ab1SVikas Manocha enum mr_attr mr_attr; 62*96b61ab1SVikas Manocha enum size reg_size; 63*96b61ab1SVikas Manocha }; 64*96b61ab1SVikas Manocha 65*96b61ab1SVikas Manocha void disable_mpu(void); 66*96b61ab1SVikas Manocha void enable_mpu(void); 67*96b61ab1SVikas Manocha void mpu_config(struct mpu_region_config *reg_config); 68