12c451f78SAneesh V /* 22c451f78SAneesh V * (C) Copyright 2010 32c451f78SAneesh V * Texas Instruments, <www.ti.com> 42c451f78SAneesh V * Aneesh V <aneesh@ti.com> 52c451f78SAneesh V * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 72c451f78SAneesh V */ 82c451f78SAneesh V #ifndef ARMV7_H 92c451f78SAneesh V #define ARMV7_H 102c451f78SAneesh V 11ad577c8aSAneesh V /* Cortex-A9 revisions */ 12ad577c8aSAneesh V #define MIDR_CORTEX_A9_R0P1 0x410FC091 13ad577c8aSAneesh V #define MIDR_CORTEX_A9_R1P2 0x411FC092 14ad577c8aSAneesh V #define MIDR_CORTEX_A9_R1P3 0x411FC093 155ab12a9eSAneesh V #define MIDR_CORTEX_A9_R2P10 0x412FC09A 16ad577c8aSAneesh V 17508a58faSSricharan /* Cortex-A15 revisions */ 18508a58faSSricharan #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 19eed7c0f7SSRICHARAN R #define MIDR_CORTEX_A15_R2P2 0x412FC0F2 20508a58faSSricharan 2116212b59SAndre Przywara /* Cortex-A7 revisions */ 2216212b59SAndre Przywara #define MIDR_CORTEX_A7_R0P0 0x410FC070 2316212b59SAndre Przywara 2416212b59SAndre Przywara #define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0 2516212b59SAndre Przywara 2616212b59SAndre Przywara /* ID_PFR1 feature fields */ 2716212b59SAndre Przywara #define CPUID_ARM_SEC_SHIFT 4 2816212b59SAndre Przywara #define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT) 2916212b59SAndre Przywara #define CPUID_ARM_VIRT_SHIFT 12 3016212b59SAndre Przywara #define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT) 3116212b59SAndre Przywara #define CPUID_ARM_GENTIMER_SHIFT 16 3216212b59SAndre Przywara #define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT) 3316212b59SAndre Przywara 3416212b59SAndre Przywara /* valid bits in CBAR register / PERIPHBASE value */ 3516212b59SAndre Przywara #define CBAR_MASK 0xFFFF8000 3616212b59SAndre Przywara 372c451f78SAneesh V /* CCSIDR */ 382c451f78SAneesh V #define CCSIDR_LINE_SIZE_OFFSET 0 392c451f78SAneesh V #define CCSIDR_LINE_SIZE_MASK 0x7 402c451f78SAneesh V #define CCSIDR_ASSOCIATIVITY_OFFSET 3 412c451f78SAneesh V #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) 422c451f78SAneesh V #define CCSIDR_NUM_SETS_OFFSET 13 432c451f78SAneesh V #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) 442c451f78SAneesh V 452c451f78SAneesh V /* 462c451f78SAneesh V * Values for InD field in CSSELR 472c451f78SAneesh V * Selects the type of cache 482c451f78SAneesh V */ 492c451f78SAneesh V #define ARMV7_CSSELR_IND_DATA_UNIFIED 0 502c451f78SAneesh V #define ARMV7_CSSELR_IND_INSTRUCTION 1 512c451f78SAneesh V 522c451f78SAneesh V /* Values for Ctype fields in CLIDR */ 532c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_NO_CACHE 0 542c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 552c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 562c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 572c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_UNIFIED 4 582c451f78SAneesh V 59d75ba503SAndre Przywara #ifndef __ASSEMBLY__ 60d75ba503SAndre Przywara #include <linux/types.h> 61d75ba503SAndre Przywara 622c451f78SAneesh V /* 632c451f78SAneesh V * CP15 Barrier instructions 642c451f78SAneesh V * Please note that we have separate barrier instructions in ARMv7 652c451f78SAneesh V * However, we use the CP15 based instructtions because we use 662c451f78SAneesh V * -march=armv5 in U-Boot 672c451f78SAneesh V */ 682c451f78SAneesh V #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) 692c451f78SAneesh V #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) 702c451f78SAneesh V #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) 712c451f78SAneesh V 722c451f78SAneesh V void v7_outer_cache_enable(void); 732c451f78SAneesh V void v7_outer_cache_disable(void); 742c451f78SAneesh V void v7_outer_cache_flush_all(void); 752c451f78SAneesh V void v7_outer_cache_inval_all(void); 762c451f78SAneesh V void v7_outer_cache_flush_range(u32 start, u32 end); 772c451f78SAneesh V void v7_outer_cache_inval_range(u32 start, u32 end); 782c451f78SAneesh V 79d4296887SAndre Przywara #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) 801ef92385SAndre Przywara 81f510aeaeSMarc Zyngier int armv7_init_nonsec(void); 82e771a3d5SMarc Zyngier int armv7_update_dt(void *fdt); 83*97a81964SIan Campbell bool armv7_boot_nonsec(void); 841ef92385SAndre Przywara 8516212b59SAndre Przywara /* defined in assembly file */ 8616212b59SAndre Przywara unsigned int _nonsec_init(void); 87f510aeaeSMarc Zyngier void _do_nonsec_entry(void *target_pc, unsigned long r0, 88f510aeaeSMarc Zyngier unsigned long r1, unsigned long r2); 89ba6a1698SAndre Przywara void _smp_pen(void); 90f510aeaeSMarc Zyngier 91f510aeaeSMarc Zyngier extern char __secure_start[]; 92f510aeaeSMarc Zyngier extern char __secure_end[]; 93f510aeaeSMarc Zyngier 94d4296887SAndre Przywara #endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */ 9516212b59SAndre Przywara 96d75ba503SAndre Przywara #endif /* ! __ASSEMBLY__ */ 97d75ba503SAndre Przywara 982c451f78SAneesh V #endif 99