12c451f78SAneesh V /* 22c451f78SAneesh V * (C) Copyright 2010 32c451f78SAneesh V * Texas Instruments, <www.ti.com> 42c451f78SAneesh V * Aneesh V <aneesh@ti.com> 52c451f78SAneesh V * 62c451f78SAneesh V * See file CREDITS for list of people who contributed to this 72c451f78SAneesh V * project. 82c451f78SAneesh V * 92c451f78SAneesh V * This program is free software; you can redistribute it and/or 102c451f78SAneesh V * modify it under the terms of the GNU General Public License as 112c451f78SAneesh V * published by the Free Software Foundation; either version 2 of 122c451f78SAneesh V * the License, or (at your option) any later version. 132c451f78SAneesh V * 142c451f78SAneesh V * This program is distributed in the hope that it will be useful, 152c451f78SAneesh V * but WITHOUT ANY WARRANTY; without even the implied warranty of 162c451f78SAneesh V * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 172c451f78SAneesh V * GNU General Public License for more details. 182c451f78SAneesh V * 192c451f78SAneesh V * You should have received a copy of the GNU General Public License 202c451f78SAneesh V * along with this program; if not, write to the Free Software 212c451f78SAneesh V * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 222c451f78SAneesh V * MA 02111-1307 USA 232c451f78SAneesh V */ 242c451f78SAneesh V #ifndef ARMV7_H 252c451f78SAneesh V #define ARMV7_H 262c451f78SAneesh V #include <linux/types.h> 272c451f78SAneesh V 28ad577c8aSAneesh V /* Cortex-A9 revisions */ 29ad577c8aSAneesh V #define MIDR_CORTEX_A9_R0P1 0x410FC091 30ad577c8aSAneesh V #define MIDR_CORTEX_A9_R1P2 0x411FC092 31ad577c8aSAneesh V #define MIDR_CORTEX_A9_R1P3 0x411FC093 32*5ab12a9eSAneesh V #define MIDR_CORTEX_A9_R2P10 0x412FC09A 33ad577c8aSAneesh V 342c451f78SAneesh V /* CCSIDR */ 352c451f78SAneesh V #define CCSIDR_LINE_SIZE_OFFSET 0 362c451f78SAneesh V #define CCSIDR_LINE_SIZE_MASK 0x7 372c451f78SAneesh V #define CCSIDR_ASSOCIATIVITY_OFFSET 3 382c451f78SAneesh V #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) 392c451f78SAneesh V #define CCSIDR_NUM_SETS_OFFSET 13 402c451f78SAneesh V #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) 412c451f78SAneesh V 422c451f78SAneesh V /* 432c451f78SAneesh V * Values for InD field in CSSELR 442c451f78SAneesh V * Selects the type of cache 452c451f78SAneesh V */ 462c451f78SAneesh V #define ARMV7_CSSELR_IND_DATA_UNIFIED 0 472c451f78SAneesh V #define ARMV7_CSSELR_IND_INSTRUCTION 1 482c451f78SAneesh V 492c451f78SAneesh V /* Values for Ctype fields in CLIDR */ 502c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_NO_CACHE 0 512c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 522c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 532c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 542c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_UNIFIED 4 552c451f78SAneesh V 562c451f78SAneesh V /* 572c451f78SAneesh V * CP15 Barrier instructions 582c451f78SAneesh V * Please note that we have separate barrier instructions in ARMv7 592c451f78SAneesh V * However, we use the CP15 based instructtions because we use 602c451f78SAneesh V * -march=armv5 in U-Boot 612c451f78SAneesh V */ 622c451f78SAneesh V #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) 632c451f78SAneesh V #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) 642c451f78SAneesh V #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) 652c451f78SAneesh V 662c451f78SAneesh V void v7_outer_cache_enable(void); 672c451f78SAneesh V void v7_outer_cache_disable(void); 682c451f78SAneesh V void v7_outer_cache_flush_all(void); 692c451f78SAneesh V void v7_outer_cache_inval_all(void); 702c451f78SAneesh V void v7_outer_cache_flush_range(u32 start, u32 end); 712c451f78SAneesh V void v7_outer_cache_inval_range(u32 start, u32 end); 722c451f78SAneesh V 732c451f78SAneesh V #endif 74