1*2c451f78SAneesh V /* 2*2c451f78SAneesh V * (C) Copyright 2010 3*2c451f78SAneesh V * Texas Instruments, <www.ti.com> 4*2c451f78SAneesh V * Aneesh V <aneesh@ti.com> 5*2c451f78SAneesh V * 6*2c451f78SAneesh V * See file CREDITS for list of people who contributed to this 7*2c451f78SAneesh V * project. 8*2c451f78SAneesh V * 9*2c451f78SAneesh V * This program is free software; you can redistribute it and/or 10*2c451f78SAneesh V * modify it under the terms of the GNU General Public License as 11*2c451f78SAneesh V * published by the Free Software Foundation; either version 2 of 12*2c451f78SAneesh V * the License, or (at your option) any later version. 13*2c451f78SAneesh V * 14*2c451f78SAneesh V * This program is distributed in the hope that it will be useful, 15*2c451f78SAneesh V * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*2c451f78SAneesh V * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*2c451f78SAneesh V * GNU General Public License for more details. 18*2c451f78SAneesh V * 19*2c451f78SAneesh V * You should have received a copy of the GNU General Public License 20*2c451f78SAneesh V * along with this program; if not, write to the Free Software 21*2c451f78SAneesh V * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*2c451f78SAneesh V * MA 02111-1307 USA 23*2c451f78SAneesh V */ 24*2c451f78SAneesh V #ifndef ARMV7_H 25*2c451f78SAneesh V #define ARMV7_H 26*2c451f78SAneesh V #include <linux/types.h> 27*2c451f78SAneesh V 28*2c451f78SAneesh V /* CCSIDR */ 29*2c451f78SAneesh V #define CCSIDR_LINE_SIZE_OFFSET 0 30*2c451f78SAneesh V #define CCSIDR_LINE_SIZE_MASK 0x7 31*2c451f78SAneesh V #define CCSIDR_ASSOCIATIVITY_OFFSET 3 32*2c451f78SAneesh V #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) 33*2c451f78SAneesh V #define CCSIDR_NUM_SETS_OFFSET 13 34*2c451f78SAneesh V #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) 35*2c451f78SAneesh V 36*2c451f78SAneesh V /* 37*2c451f78SAneesh V * Values for InD field in CSSELR 38*2c451f78SAneesh V * Selects the type of cache 39*2c451f78SAneesh V */ 40*2c451f78SAneesh V #define ARMV7_CSSELR_IND_DATA_UNIFIED 0 41*2c451f78SAneesh V #define ARMV7_CSSELR_IND_INSTRUCTION 1 42*2c451f78SAneesh V 43*2c451f78SAneesh V /* Values for Ctype fields in CLIDR */ 44*2c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_NO_CACHE 0 45*2c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 46*2c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 47*2c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 48*2c451f78SAneesh V #define ARMV7_CLIDR_CTYPE_UNIFIED 4 49*2c451f78SAneesh V 50*2c451f78SAneesh V /* 51*2c451f78SAneesh V * CP15 Barrier instructions 52*2c451f78SAneesh V * Please note that we have separate barrier instructions in ARMv7 53*2c451f78SAneesh V * However, we use the CP15 based instructtions because we use 54*2c451f78SAneesh V * -march=armv5 in U-Boot 55*2c451f78SAneesh V */ 56*2c451f78SAneesh V #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) 57*2c451f78SAneesh V #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) 58*2c451f78SAneesh V #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) 59*2c451f78SAneesh V 60*2c451f78SAneesh V void v7_outer_cache_enable(void); 61*2c451f78SAneesh V void v7_outer_cache_disable(void); 62*2c451f78SAneesh V void v7_outer_cache_flush_all(void); 63*2c451f78SAneesh V void v7_outer_cache_inval_all(void); 64*2c451f78SAneesh V void v7_outer_cache_flush_range(u32 start, u32 end); 65*2c451f78SAneesh V void v7_outer_cache_inval_range(u32 start, u32 end); 66*2c451f78SAneesh V 67*2c451f78SAneesh V #endif 68