1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_SYS_PROTO_H 9 #define _ASM_ARCH_SYS_PROTO_H 10 11 #ifndef CONFIG_CLK_ZYNQMP 12 /* Setup clk for network */ 13 static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) 14 { 15 } 16 #endif 17 18 int zynq_slcr_get_mio_pin_status(const char *periph); 19 20 unsigned int zynqmp_get_silicon_version(void); 21 22 void psu_init(void); 23 24 void handoff_setup(void); 25 26 #endif /* _ASM_ARCH_SYS_PROTO_H */ 27