184c7204bSMichal Simek /* 284c7204bSMichal Simek * (C) Copyright 2014 - 2015 Xilinx, Inc. 384c7204bSMichal Simek * Michal Simek <michal.simek@xilinx.com> 484c7204bSMichal Simek * 584c7204bSMichal Simek * SPDX-License-Identifier: GPL-2.0+ 684c7204bSMichal Simek */ 784c7204bSMichal Simek 884c7204bSMichal Simek #ifndef _ASM_ARCH_SYS_PROTO_H 984c7204bSMichal Simek #define _ASM_ARCH_SYS_PROTO_H 1084c7204bSMichal Simek 11cb7ea820SMichal Simek /* Setup clk for network */ 12cb7ea820SMichal Simek static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) 13cb7ea820SMichal Simek { 14cb7ea820SMichal Simek } 15cb7ea820SMichal Simek 16225bf9aaSMichal Simek int zynq_slcr_get_mio_pin_status(const char *periph); 1784c7204bSMichal Simek 1884c7204bSMichal Simek unsigned int zynqmp_get_silicon_version(void); 1984c7204bSMichal Simek 20*e6a9ed04SMichal Simek void psu_init(void); 21*e6a9ed04SMichal Simek 2284c7204bSMichal Simek #endif /* _ASM_ARCH_SYS_PROTO_H */ 23