1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_HARDWARE_H 9 #define _ASM_ARCH_HARDWARE_H 10 11 #define ZYNQ_SERIAL_BASEADDR0 0xFF000000 12 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000 13 14 #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 15 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 16 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 17 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000 18 19 #define ZYNQ_SPI_BASEADDR0 0xFF040000 20 #define ZYNQ_SPI_BASEADDR1 0xFF050000 21 22 #define ZYNQ_I2C_BASEADDR0 0xFF020000 23 #define ZYNQ_I2C_BASEADDR1 0xFF030000 24 25 #define ZYNQ_SDHCI_BASEADDR0 0xFF160000 26 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000 27 28 #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 29 30 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 31 #define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000 32 33 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 34 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 35 36 struct crlapb_regs { 37 u32 reserved0[36]; 38 u32 cpu_r5_ctrl; /* 0x90 */ 39 u32 reserved1[37]; 40 u32 timestamp_ref_ctrl; /* 0x128 */ 41 u32 reserved2[53]; 42 u32 boot_mode; /* 0x200 */ 43 u32 reserved3[14]; 44 u32 rst_lpd_top; /* 0x23C */ 45 u32 reserved4[26]; 46 }; 47 48 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 49 50 #if defined(CONFIG_SECURE_IOU) 51 #define ZYNQMP_IOU_SCNTR 0xFF260000 52 #else 53 #define ZYNQMP_IOU_SCNTR 0xFF250000 54 #endif 55 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 56 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 57 58 struct iou_scntr { 59 u32 counter_control_register; 60 u32 reserved0[7]; 61 u32 base_frequency_id_register; 62 }; 63 64 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) 65 66 /* Bootmode setting values */ 67 #define BOOT_MODES_MASK 0x0000000F 68 #define SD_MODE 0x00000003 69 #define EMMC_MODE 0x00000006 70 #define JTAG_MODE 0x00000000 71 72 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 73 74 struct iou_slcr_regs { 75 u32 mio_pin[78]; 76 u32 reserved[442]; 77 }; 78 79 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 80 81 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 82 83 struct rpu_regs { 84 u32 rpu_glbl_ctrl; 85 u32 reserved0[63]; 86 u32 rpu0_cfg; /* 0x100 */ 87 u32 reserved1[63]; 88 u32 rpu1_cfg; /* 0x200 */ 89 }; 90 91 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 92 93 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 94 95 struct crfapb_regs { 96 u32 reserved0[65]; 97 u32 rst_fpd_apu; /* 0x104 */ 98 u32 reserved1; 99 }; 100 101 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 102 103 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 104 105 struct apu_regs { 106 u32 reserved0[16]; 107 u32 rvbar_addr0_l; /* 0x40 */ 108 u32 rvbar_addr0_h; /* 0x44 */ 109 u32 reserved1[20]; 110 }; 111 112 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 113 114 /* Board version value */ 115 #define ZYNQMP_CSU_VERSION_SILICON 0x0 116 #define ZYNQMP_CSU_VERSION_EP108 0x1 117 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 118 #define ZYNQMP_CSU_VERSION_QEMU 0x3 119 120 #endif /* _ASM_ARCH_HARDWARE_H */ 121