1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_HARDWARE_H 9 #define _ASM_ARCH_HARDWARE_H 10 11 #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 12 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 13 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 14 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000 15 16 #define ZYNQ_I2C_BASEADDR0 0xFF020000 17 #define ZYNQ_I2C_BASEADDR1 0xFF030000 18 19 #define ARASAN_NAND_BASEADDR 0xFF100000 20 21 #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 22 23 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 24 #define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000 25 26 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 27 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 28 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 29 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 30 31 #define PS_MODE0 BIT(0) 32 #define PS_MODE1 BIT(1) 33 #define PS_MODE2 BIT(2) 34 #define PS_MODE3 BIT(3) 35 36 struct crlapb_regs { 37 u32 reserved0[36]; 38 u32 cpu_r5_ctrl; /* 0x90 */ 39 u32 reserved1[37]; 40 u32 timestamp_ref_ctrl; /* 0x128 */ 41 u32 reserved2[53]; 42 u32 boot_mode; /* 0x200 */ 43 u32 reserved3[14]; 44 u32 rst_lpd_top; /* 0x23C */ 45 u32 reserved4[4]; 46 u32 boot_pin_ctrl; /* 0x250 */ 47 u32 reserved5[21]; 48 }; 49 50 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 51 52 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 53 #define ZYNQMP_IOU_SCNTR 0xFF250000 54 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 55 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 56 57 struct iou_scntr { 58 u32 counter_control_register; 59 u32 reserved0[7]; 60 u32 base_frequency_id_register; 61 }; 62 63 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) 64 65 struct iou_scntr_secure { 66 u32 counter_control_register; 67 u32 reserved0[7]; 68 u32 base_frequency_id_register; 69 }; 70 71 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 72 73 /* Bootmode setting values */ 74 #define BOOT_MODES_MASK 0x0000000F 75 #define QSPI_MODE_24BIT 0x00000001 76 #define QSPI_MODE_32BIT 0x00000002 77 #define SD_MODE 0x00000003 /* sd 0 */ 78 #define SD_MODE1 0x00000005 /* sd 1 */ 79 #define NAND_MODE 0x00000004 80 #define EMMC_MODE 0x00000006 81 #define USB_MODE 0x00000007 82 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 83 #define JTAG_MODE 0x00000000 84 #define BOOT_MODE_USE_ALT 0x100 85 #define BOOT_MODE_ALT_SHIFT 12 86 /* SW secondary boot modes 0xa - 0xd */ 87 #define SW_USBHOST_MODE 0x0000000A 88 #define SW_SATA_MODE 0x0000000B 89 90 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 91 92 struct iou_slcr_regs { 93 u32 mio_pin[78]; 94 u32 reserved[442]; 95 }; 96 97 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 98 99 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 100 101 struct rpu_regs { 102 u32 rpu_glbl_ctrl; 103 u32 reserved0[63]; 104 u32 rpu0_cfg; /* 0x100 */ 105 u32 reserved1[63]; 106 u32 rpu1_cfg; /* 0x200 */ 107 }; 108 109 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 110 111 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 112 113 struct crfapb_regs { 114 u32 reserved0[65]; 115 u32 rst_fpd_apu; /* 0x104 */ 116 u32 reserved1; 117 }; 118 119 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 120 121 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 122 123 struct apu_regs { 124 u32 reserved0[16]; 125 u32 rvbar_addr0_l; /* 0x40 */ 126 u32 rvbar_addr0_h; /* 0x44 */ 127 u32 reserved1[20]; 128 }; 129 130 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 131 132 /* Board version value */ 133 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 134 #define ZYNQMP_CSU_VERSION_SILICON 0x0 135 #define ZYNQMP_CSU_VERSION_EP108 0x1 136 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 137 #define ZYNQMP_CSU_VERSION_QEMU 0x3 138 139 #define ZYNQMP_SILICON_VER_MASK 0xF000 140 #define ZYNQMP_SILICON_VER_SHIFT 12 141 142 struct csu_regs { 143 u32 reserved0[17]; 144 u32 version; 145 }; 146 147 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 148 149 #endif /* _ASM_ARCH_HARDWARE_H */ 150