1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_HARDWARE_H 9 #define _ASM_ARCH_HARDWARE_H 10 11 #define ZYNQ_SERIAL_BASEADDR0 0xFF000000 12 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000 13 14 #define ZYNQ_SDHCI_BASEADDR0 0xFF160000 15 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000 16 17 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 18 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 19 20 struct crlapb_regs { 21 u32 reserved0[36]; 22 u32 cpu_r5_ctrl; /* 0x90 */ 23 u32 reserved1[37]; 24 u32 timestamp_ref_ctrl; /* 0x128 */ 25 u32 reserved2[53]; 26 u32 boot_mode; /* 0x200 */ 27 u32 reserved3[14]; 28 u32 rst_lpd_top; /* 0x23C */ 29 u32 reserved4[26]; 30 }; 31 32 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 33 34 #define ZYNQMP_IOU_SCNTR 0xFF250000 35 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 36 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 37 38 struct iou_scntr { 39 u32 counter_control_register; 40 u32 reserved0[7]; 41 u32 base_frequency_id_register; 42 }; 43 44 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) 45 46 /* Bootmode setting values */ 47 #define BOOT_MODES_MASK 0x0000000F 48 #define SD_MODE 0x00000005 49 #define JTAG_MODE 0x00000000 50 51 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 52 53 struct rpu_regs { 54 u32 rpu_glbl_ctrl; 55 u32 reserved0[63]; 56 u32 rpu0_cfg; /* 0x100 */ 57 u32 reserved1[63]; 58 u32 rpu1_cfg; /* 0x200 */ 59 }; 60 61 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 62 63 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 64 65 struct crfapb_regs { 66 u32 reserved0[65]; 67 u32 rst_fpd_apu; /* 0x104 */ 68 u32 reserved1; 69 }; 70 71 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 72 73 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 74 75 struct apu_regs { 76 u32 reserved0[16]; 77 u32 rvbar_addr0_l; /* 0x40 */ 78 u32 rvbar_addr0_h; /* 0x44 */ 79 u32 reserved1[20]; 80 }; 81 82 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 83 84 /* Board version value */ 85 #define ZYNQMP_CSU_VERSION_SILICON 0x0 86 #define ZYNQMP_CSU_VERSION_EP108 0x1 87 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 88 #define ZYNQMP_CSU_VERSION_QEMU 0x3 89 90 #endif /* _ASM_ARCH_HARDWARE_H */ 91