1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_HARDWARE_H 9 #define _ASM_ARCH_HARDWARE_H 10 11 #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 12 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 13 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 14 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000 15 16 #define ZYNQ_SPI_BASEADDR0 0xFF040000 17 #define ZYNQ_SPI_BASEADDR1 0xFF050000 18 19 #define ZYNQ_I2C_BASEADDR0 0xFF020000 20 #define ZYNQ_I2C_BASEADDR1 0xFF030000 21 22 #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 23 24 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 25 #define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000 26 27 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 28 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 29 30 struct crlapb_regs { 31 u32 reserved0[36]; 32 u32 cpu_r5_ctrl; /* 0x90 */ 33 u32 reserved1[37]; 34 u32 timestamp_ref_ctrl; /* 0x128 */ 35 u32 reserved2[53]; 36 u32 boot_mode; /* 0x200 */ 37 u32 reserved3[14]; 38 u32 rst_lpd_top; /* 0x23C */ 39 u32 reserved4[26]; 40 }; 41 42 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 43 44 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 45 #define ZYNQMP_IOU_SCNTR 0xFF250000 46 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 47 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 48 49 struct iou_scntr { 50 u32 counter_control_register; 51 u32 reserved0[7]; 52 u32 base_frequency_id_register; 53 }; 54 55 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) 56 57 struct iou_scntr_secure { 58 u32 counter_control_register; 59 u32 reserved0[7]; 60 u32 base_frequency_id_register; 61 }; 62 63 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 64 65 /* Bootmode setting values */ 66 #define BOOT_MODES_MASK 0x0000000F 67 #define SD_MODE 0x00000003 68 #define EMMC_MODE 0x00000006 69 #define JTAG_MODE 0x00000000 70 71 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 72 73 struct iou_slcr_regs { 74 u32 mio_pin[78]; 75 u32 reserved[442]; 76 }; 77 78 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 79 80 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 81 82 struct rpu_regs { 83 u32 rpu_glbl_ctrl; 84 u32 reserved0[63]; 85 u32 rpu0_cfg; /* 0x100 */ 86 u32 reserved1[63]; 87 u32 rpu1_cfg; /* 0x200 */ 88 }; 89 90 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 91 92 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 93 94 struct crfapb_regs { 95 u32 reserved0[65]; 96 u32 rst_fpd_apu; /* 0x104 */ 97 u32 reserved1; 98 }; 99 100 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 101 102 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 103 104 struct apu_regs { 105 u32 reserved0[16]; 106 u32 rvbar_addr0_l; /* 0x40 */ 107 u32 rvbar_addr0_h; /* 0x44 */ 108 u32 reserved1[20]; 109 }; 110 111 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 112 113 /* Board version value */ 114 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 115 #define ZYNQMP_CSU_VERSION_SILICON 0x0 116 #define ZYNQMP_CSU_VERSION_EP108 0x1 117 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 118 #define ZYNQMP_CSU_VERSION_QEMU 0x3 119 120 #define ZYNQMP_SILICON_VER_MASK 0xF000 121 #define ZYNQMP_SILICON_VER_SHIFT 12 122 123 struct csu_regs { 124 u32 reserved0[17]; 125 u32 version; 126 }; 127 128 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 129 130 #endif /* _ASM_ARCH_HARDWARE_H */ 131