xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-zynqmp/clk.h (revision 9f03247edc7761b608db31104821b4518a70e691)
184c7204bSMichal Simek /*
284c7204bSMichal Simek  * (C) Copyright 2014 - 2015 Xilinx, Inc.
384c7204bSMichal Simek  * Michal Simek <michal.simek@xilinx.com>
484c7204bSMichal Simek  *
584c7204bSMichal Simek  * SPDX-License-Identifier:	GPL-2.0+
684c7204bSMichal Simek  */
784c7204bSMichal Simek 
884c7204bSMichal Simek #ifndef _ASM_ARCH_CLK_H_
984c7204bSMichal Simek #define _ASM_ARCH_CLK_H_
1084c7204bSMichal Simek 
11*0785dfd8SMichal Simek unsigned long zynqmp_get_system_timer_freq(void);
1284c7204bSMichal Simek 
1384c7204bSMichal Simek #endif /* _ASM_ARCH_CLK_H_ */
14