1*d348a943SBhuvanchandra DV /* 2*d348a943SBhuvanchandra DV * Copyright (C) 2015 3*d348a943SBhuvanchandra DV * Bhuvanchandra DV, Toradex, Inc. 4*d348a943SBhuvanchandra DV * 5*d348a943SBhuvanchandra DV * SPDX-License-Identifier: GPL-2.0 6*d348a943SBhuvanchandra DV */ 7*d348a943SBhuvanchandra DV 8*d348a943SBhuvanchandra DV #ifndef __ASM_ARCH_VF610_GPIO_H 9*d348a943SBhuvanchandra DV #define __ASM_ARCH_VF610_GPIO_H 10*d348a943SBhuvanchandra DV 11*d348a943SBhuvanchandra DV #define VYBRID_GPIO_COUNT 32 12*d348a943SBhuvanchandra DV #define VF610_GPIO_DIRECTION_IN 0x0 13*d348a943SBhuvanchandra DV #define VF610_GPIO_DIRECTION_OUT 0x1 14*d348a943SBhuvanchandra DV 15*d348a943SBhuvanchandra DV /* GPIO registers */ 16*d348a943SBhuvanchandra DV struct vybrid_gpio_regs { 17*d348a943SBhuvanchandra DV u32 gpio_pdor; 18*d348a943SBhuvanchandra DV u32 gpio_psor; 19*d348a943SBhuvanchandra DV u32 gpio_pcor; 20*d348a943SBhuvanchandra DV u32 gpio_ptor; 21*d348a943SBhuvanchandra DV u32 gpio_pdir; 22*d348a943SBhuvanchandra DV }; 23*d348a943SBhuvanchandra DV 24*d348a943SBhuvanchandra DV struct vybrid_gpio_platdata { 25*d348a943SBhuvanchandra DV unsigned int chip; 26*d348a943SBhuvanchandra DV u32 base; 27*d348a943SBhuvanchandra DV const char *port_name; 28*d348a943SBhuvanchandra DV }; 29*d348a943SBhuvanchandra DV #endif /* __ASM_ARCH_VF610_GPIO_H */ 30