1dc89ad14STom Warren /* 2dc89ad14STom Warren * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 3dc89ad14STom Warren * 4*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 5dc89ad14STom Warren */ 6dc89ad14STom Warren 7dc89ad14STom Warren #ifndef _TEGRA30_GP_PADCTRL_H_ 8dc89ad14STom Warren #define _TEGRA30_GP_PADCTRL_H_ 9dc89ad14STom Warren 10dc89ad14STom Warren #include <asm/arch-tegra/gp_padctrl.h> 11dc89ad14STom Warren 12dc89ad14STom Warren /* APB_MISC_GP and padctrl registers */ 13dc89ad14STom Warren struct apb_misc_gp_ctlr { 14dc89ad14STom Warren u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 15dc89ad14STom Warren u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 16dc89ad14STom Warren u32 reserved0[22]; /* 0x08 - 0x5C: */ 17dc89ad14STom Warren u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 18dc89ad14STom Warren u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 19dc89ad14STom Warren u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 20dc89ad14STom Warren u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ 21dc89ad14STom Warren u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 22dc89ad14STom Warren u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 23dc89ad14STom Warren u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ 24dc89ad14STom Warren u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ 25dc89ad14STom Warren u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ 26dc89ad14STom Warren u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ 27dc89ad14STom Warren u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ 28dc89ad14STom Warren u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ 29dc89ad14STom Warren u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ 30dc89ad14STom Warren u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ 31dc89ad14STom Warren u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ 32dc89ad14STom Warren u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ 33dc89ad14STom Warren u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ 34dc89ad14STom Warren u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ 35dc89ad14STom Warren u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ 36dc89ad14STom Warren u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ 37dc89ad14STom Warren u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ 38dc89ad14STom Warren u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ 39dc89ad14STom Warren u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ 40dc89ad14STom Warren u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ 41dc89ad14STom Warren u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ 42dc89ad14STom Warren u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ 43dc89ad14STom Warren u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ 44dc89ad14STom Warren u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ 45dc89ad14STom Warren u32 reserved1[7]; /* 0xD0-0xE8: */ 46dc89ad14STom Warren u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ 47dc89ad14STom Warren }; 48dc89ad14STom Warren 498ca79b2fSTom Warren /* SDMMC1/3 settings from section 24.6 of T30 TRM */ 508ca79b2fSTom Warren #define SDIOCFG_DRVUP_SLWF 1 518ca79b2fSTom Warren #define SDIOCFG_DRVDN_SLWR 1 528ca79b2fSTom Warren #define SDIOCFG_DRVUP 0x2E 538ca79b2fSTom Warren #define SDIOCFG_DRVDN 0x2A 548ca79b2fSTom Warren 55dc89ad14STom Warren #endif /* _TEGRA30_GP_PADCTRL_H_ */ 56