1dc89ad14STom Warren /* 2dc89ad14STom Warren * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 3dc89ad14STom Warren * 4*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 5dc89ad14STom Warren */ 6dc89ad14STom Warren 7dc89ad14STom Warren /* Tegra30 clock control functions */ 8dc89ad14STom Warren 9dc89ad14STom Warren #ifndef _TEGRA30_CLOCK_H_ 10dc89ad14STom Warren #define _TEGRA30_CLOCK_H_ 11dc89ad14STom Warren 12dc89ad14STom Warren #include <asm/arch-tegra/clock.h> 13dc89ad14STom Warren 14f29f086aSTom Warren /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 15f29f086aSTom Warren #define OSC_FREQ_SHIFT 28 16f29f086aSTom Warren #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) 17f29f086aSTom Warren 18a7230745SThierry Reding int tegra_plle_enable(void); 19a7230745SThierry Reding 20dc89ad14STom Warren #endif /* _TEGRA30_CLOCK_H_ */ 21