1*6c43f6c8STom Warren /* 2*6c43f6c8STom Warren * (C) Copyright 2013-2015 3*6c43f6c8STom Warren * NVIDIA Corporation <www.nvidia.com> 4*6c43f6c8STom Warren * 5*6c43f6c8STom Warren * SPDX-License-Identifier: GPL-2.0+ 6*6c43f6c8STom Warren */ 7*6c43f6c8STom Warren 8*6c43f6c8STom Warren #ifndef _TEGRA210_SYSCTR_H_ 9*6c43f6c8STom Warren #define _TEGRA210_SYSCTR_H_ 10*6c43f6c8STom Warren 11*6c43f6c8STom Warren struct sysctr_ctlr { 12*6c43f6c8STom Warren u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ 13*6c43f6c8STom Warren u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ 14*6c43f6c8STom Warren u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ 15*6c43f6c8STom Warren u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ 16*6c43f6c8STom Warren u32 reserved1[4]; /* 0x10 - 0x1C */ 17*6c43f6c8STom Warren u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ 18*6c43f6c8STom Warren u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ 19*6c43f6c8STom Warren u32 reserved2[1002]; /* 0x28 - 0xFCC */ 20*6c43f6c8STom Warren u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ 21*6c43f6c8STom Warren }; 22*6c43f6c8STom Warren 23*6c43f6c8STom Warren #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ 24*6c43f6c8STom Warren #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ 25*6c43f6c8STom Warren 26*6c43f6c8STom Warren #endif /* _TEGRA210_SYSCTR_H_ */ 27