1*6c43f6c8STom Warren /* 2*6c43f6c8STom Warren * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. 3*6c43f6c8STom Warren * 4*6c43f6c8STom Warren * SPDX-License-Identifier: GPL-2.0+ 5*6c43f6c8STom Warren */ 6*6c43f6c8STom Warren 7*6c43f6c8STom Warren #ifndef _TEGRA210_MC_H_ 8*6c43f6c8STom Warren #define _TEGRA210_MC_H_ 9*6c43f6c8STom Warren 10*6c43f6c8STom Warren /** 11*6c43f6c8STom Warren * Defines the memory controller registers we need/care about 12*6c43f6c8STom Warren */ 13*6c43f6c8STom Warren struct mc_ctlr { 14*6c43f6c8STom Warren u32 reserved0[4]; /* offset 0x00 - 0x0C */ 15*6c43f6c8STom Warren u32 mc_smmu_config; /* offset 0x10 */ 16*6c43f6c8STom Warren u32 mc_smmu_tlb_config; /* offset 0x14 */ 17*6c43f6c8STom Warren u32 mc_smmu_ptc_config; /* offset 0x18 */ 18*6c43f6c8STom Warren u32 mc_smmu_ptb_asid; /* offset 0x1C */ 19*6c43f6c8STom Warren u32 mc_smmu_ptb_data; /* offset 0x20 */ 20*6c43f6c8STom Warren u32 reserved1[3]; /* offset 0x24 - 0x2C */ 21*6c43f6c8STom Warren u32 mc_smmu_tlb_flush; /* offset 0x30 */ 22*6c43f6c8STom Warren u32 mc_smmu_ptc_flush; /* offset 0x34 */ 23*6c43f6c8STom Warren u32 reserved2[6]; /* offset 0x38 - 0x4C */ 24*6c43f6c8STom Warren u32 mc_emem_cfg; /* offset 0x50 */ 25*6c43f6c8STom Warren u32 mc_emem_adr_cfg; /* offset 0x54 */ 26*6c43f6c8STom Warren u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ 27*6c43f6c8STom Warren u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ 28*6c43f6c8STom Warren u32 reserved3[4]; /* offset 0x60 - 0x6C */ 29*6c43f6c8STom Warren u32 mc_security_cfg0; /* offset 0x70 */ 30*6c43f6c8STom Warren u32 mc_security_cfg1; /* offset 0x74 */ 31*6c43f6c8STom Warren u32 reserved4[6]; /* offset 0x7C - 0x8C */ 32*6c43f6c8STom Warren u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ 33*6c43f6c8STom Warren u32 reserved5[74]; /* offset 0x100 - 0x224 */ 34*6c43f6c8STom Warren u32 mc_smmu_translation_enable_0; /* offset 0x228 */ 35*6c43f6c8STom Warren u32 mc_smmu_translation_enable_1; /* offset 0x22C */ 36*6c43f6c8STom Warren u32 mc_smmu_translation_enable_2; /* offset 0x230 */ 37*6c43f6c8STom Warren u32 mc_smmu_translation_enable_3; /* offset 0x234 */ 38*6c43f6c8STom Warren u32 mc_smmu_afi_asid; /* offset 0x238 */ 39*6c43f6c8STom Warren u32 mc_smmu_avpc_asid; /* offset 0x23C */ 40*6c43f6c8STom Warren u32 mc_smmu_dc_asid; /* offset 0x240 */ 41*6c43f6c8STom Warren u32 mc_smmu_dcb_asid; /* offset 0x244 */ 42*6c43f6c8STom Warren u32 reserved6[2]; /* offset 0x248 - 0x24C */ 43*6c43f6c8STom Warren u32 mc_smmu_hc_asid; /* offset 0x250 */ 44*6c43f6c8STom Warren u32 mc_smmu_hda_asid; /* offset 0x254 */ 45*6c43f6c8STom Warren u32 mc_smmu_isp2_asid; /* offset 0x258 */ 46*6c43f6c8STom Warren u32 reserved7[2]; /* offset 0x25C - 0x260 */ 47*6c43f6c8STom Warren u32 mc_smmu_msenc_asid; /* offset 0x264 */ 48*6c43f6c8STom Warren u32 mc_smmu_nv_asid; /* offset 0x268 */ 49*6c43f6c8STom Warren u32 mc_smmu_nv2_asid; /* offset 0x26C */ 50*6c43f6c8STom Warren u32 mc_smmu_ppcs_asid; /* offset 0x270 */ 51*6c43f6c8STom Warren u32 mc_smmu_sata_asid; /* offset 0x274 */ 52*6c43f6c8STom Warren u32 reserved8[1]; /* offset 0x278 */ 53*6c43f6c8STom Warren u32 mc_smmu_vde_asid; /* offset 0x27C */ 54*6c43f6c8STom Warren u32 mc_smmu_vi_asid; /* offset 0x280 */ 55*6c43f6c8STom Warren u32 mc_smmu_vic_asid; /* offset 0x284 */ 56*6c43f6c8STom Warren u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ 57*6c43f6c8STom Warren u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ 58*6c43f6c8STom Warren u32 reserved9[1]; /* offset 0x290 */ 59*6c43f6c8STom Warren u32 mc_smmu_tsec_asid; /* offset 0x294 */ 60*6c43f6c8STom Warren u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ 61*6c43f6c8STom Warren u32 reserved10[235]; /* offset 0x29C - 0x644 */ 62*6c43f6c8STom Warren u32 mc_video_protect_bom; /* offset 0x648 */ 63*6c43f6c8STom Warren u32 mc_video_protect_size_mb; /* offset 0x64c */ 64*6c43f6c8STom Warren u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ 65*6c43f6c8STom Warren }; 66*6c43f6c8STom Warren 67*6c43f6c8STom Warren #define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) 68*6c43f6c8STom Warren 69*6c43f6c8STom Warren #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) 70*6c43f6c8STom Warren #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) 71*6c43f6c8STom Warren 72*6c43f6c8STom Warren #endif /* _TEGRA210_MC_H_ */ 73