1*6c43f6c8STom Warren /* 2*6c43f6c8STom Warren * (C) Copyright 2010-2015 3*6c43f6c8STom Warren * NVIDIA Corporation <www.nvidia.com> 4*6c43f6c8STom Warren * 5*6c43f6c8STom Warren * SPDX-License-Identifier: GPL-2.0+ 6*6c43f6c8STom Warren */ 7*6c43f6c8STom Warren 8*6c43f6c8STom Warren #ifndef _TEGRA210_FLOW_H_ 9*6c43f6c8STom Warren #define _TEGRA210_FLOW_H_ 10*6c43f6c8STom Warren 11*6c43f6c8STom Warren struct flow_ctlr { 12*6c43f6c8STom Warren u32 halt_cpu_events; /* offset 0x00 */ 13*6c43f6c8STom Warren u32 halt_cop_events; /* offset 0x04 */ 14*6c43f6c8STom Warren u32 cpu_csr; /* offset 0x08 */ 15*6c43f6c8STom Warren u32 cop_csr; /* offset 0x0c */ 16*6c43f6c8STom Warren u32 xrq_events; /* offset 0x10 */ 17*6c43f6c8STom Warren u32 halt_cpu1_events; /* offset 0x14 */ 18*6c43f6c8STom Warren u32 cpu1_csr; /* offset 0x18 */ 19*6c43f6c8STom Warren u32 halt_cpu2_events; /* offset 0x1c */ 20*6c43f6c8STom Warren u32 cpu2_csr; /* offset 0x20 */ 21*6c43f6c8STom Warren u32 halt_cpu3_events; /* offset 0x24 */ 22*6c43f6c8STom Warren u32 cpu3_csr; /* offset 0x28 */ 23*6c43f6c8STom Warren u32 cluster_control; /* offset 0x2c */ 24*6c43f6c8STom Warren u32 halt_cop1_events; /* offset 0x30 */ 25*6c43f6c8STom Warren u32 halt_cop1_csr; /* offset 0x34 */ 26*6c43f6c8STom Warren u32 cpu_pwr_csr; /* offset 0x38 */ 27*6c43f6c8STom Warren u32 mpid; /* offset 0x3c */ 28*6c43f6c8STom Warren u32 ram_repair; /* offset 0x40 */ 29*6c43f6c8STom Warren }; 30*6c43f6c8STom Warren 31*6c43f6c8STom Warren /* HALT_COP_EVENTS_0, 0x04 */ 32*6c43f6c8STom Warren #define EVENT_MSEC (1 << 24) 33*6c43f6c8STom Warren #define EVENT_USEC (1 << 25) 34*6c43f6c8STom Warren #define EVENT_JTAG (1 << 28) 35*6c43f6c8STom Warren #define EVENT_MODE_STOP (2 << 29) 36*6c43f6c8STom Warren 37*6c43f6c8STom Warren /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ 38*6c43f6c8STom Warren #define ACTIVE_LP (1 << 0) 39*6c43f6c8STom Warren 40*6c43f6c8STom Warren /* CPUn_CSR_0 */ 41*6c43f6c8STom Warren #define CSR_ENABLE (1 << 0) 42*6c43f6c8STom Warren #define CSR_IMMEDIATE_WAKE (1 << 3) 43*6c43f6c8STom Warren #define CSR_WAIT_WFI_SHIFT 8 44*6c43f6c8STom Warren 45*6c43f6c8STom Warren #endif /* _TEGRA210_FLOW_H_ */ 46