1*6c43f6c8STom Warren /* 2*6c43f6c8STom Warren * (C) Copyright 2010-2015 3*6c43f6c8STom Warren * NVIDIA Corporation <www.nvidia.com> 4*6c43f6c8STom Warren * 5*6c43f6c8STom Warren * SPDX-License-Identifier: GPL-2.0+ 6*6c43f6c8STom Warren */ 7*6c43f6c8STom Warren 8*6c43f6c8STom Warren /* Tegra210 clock control definitions */ 9*6c43f6c8STom Warren 10*6c43f6c8STom Warren #ifndef _TEGRA210_CLOCK_H_ 11*6c43f6c8STom Warren #define _TEGRA210_CLOCK_H_ 12*6c43f6c8STom Warren 13*6c43f6c8STom Warren #include <asm/arch-tegra/clock.h> 14*6c43f6c8STom Warren 15*6c43f6c8STom Warren /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 16*6c43f6c8STom Warren #define OSC_FREQ_SHIFT 28 17*6c43f6c8STom Warren #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) 18*6c43f6c8STom Warren 19*6c43f6c8STom Warren /* PLL bits that differ from generic clk_rst.h */ 20*6c43f6c8STom Warren #define PLLC_RESET 30 21*6c43f6c8STom Warren #define PLLC_IDDQ 27 22*6c43f6c8STom Warren #define PLLD_ENABLE_CLK 21 23*6c43f6c8STom Warren #define PLLD_EN_LCKDET 28 24*6c43f6c8STom Warren 25*6c43f6c8STom Warren int tegra_plle_enable(void); 26*6c43f6c8STom Warren 27*6c43f6c8STom Warren #endif /* _TEGRA210_CLOCK_H_ */ 28