1*8c33ba7bSMarcel Ziswiler /* 2*8c33ba7bSMarcel Ziswiler * (C) Copyright 2014 3*8c33ba7bSMarcel Ziswiler * NVIDIA Corporation <www.nvidia.com> 4*8c33ba7bSMarcel Ziswiler * 5*8c33ba7bSMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+ 6*8c33ba7bSMarcel Ziswiler */ 7*8c33ba7bSMarcel Ziswiler 8*8c33ba7bSMarcel Ziswiler #ifndef _TEGRA20_MC_H_ 9*8c33ba7bSMarcel Ziswiler #define _TEGRA20_MC_H_ 10*8c33ba7bSMarcel Ziswiler 11*8c33ba7bSMarcel Ziswiler /** 12*8c33ba7bSMarcel Ziswiler * Defines the memory controller registers we need/care about 13*8c33ba7bSMarcel Ziswiler */ 14*8c33ba7bSMarcel Ziswiler struct mc_ctlr { 15*8c33ba7bSMarcel Ziswiler u32 reserved0[3]; /* offset 0x00 - 0x08 */ 16*8c33ba7bSMarcel Ziswiler u32 mc_emem_cfg; /* offset 0x0C */ 17*8c33ba7bSMarcel Ziswiler u32 mc_emem_adr_cfg; /* offset 0x10 */ 18*8c33ba7bSMarcel Ziswiler u32 mc_emem_arb_cfg0; /* offset 0x14 */ 19*8c33ba7bSMarcel Ziswiler u32 mc_emem_arb_cfg1; /* offset 0x18 */ 20*8c33ba7bSMarcel Ziswiler u32 mc_emem_arb_cfg2; /* offset 0x1C */ 21*8c33ba7bSMarcel Ziswiler u32 reserved1; /* offset 0x20 */ 22*8c33ba7bSMarcel Ziswiler u32 mc_gart_cfg; /* offset 0x24 */ 23*8c33ba7bSMarcel Ziswiler u32 mc_gart_entry_addr; /* offset 0x28 */ 24*8c33ba7bSMarcel Ziswiler u32 mc_gart_entry_data; /* offset 0x2C */ 25*8c33ba7bSMarcel Ziswiler u32 mc_gart_error_req; /* offset 0x30 */ 26*8c33ba7bSMarcel Ziswiler u32 mc_gart_error_addr; /* offset 0x34 */ 27*8c33ba7bSMarcel Ziswiler u32 reserved2; /* offset 0x38 */ 28*8c33ba7bSMarcel Ziswiler u32 mc_timeout_ctrl; /* offset 0x3C */ 29*8c33ba7bSMarcel Ziswiler u32 reserved3[6]; /* offset 0x40 - 0x54 */ 30*8c33ba7bSMarcel Ziswiler u32 mc_decerr_emem_others_status; /* offset 0x58 */ 31*8c33ba7bSMarcel Ziswiler u32 mc_decerr_emem_others_adr; /* offset 0x5C */ 32*8c33ba7bSMarcel Ziswiler u32 reserved4[40]; /* offset 0x60 - 0xFC */ 33*8c33ba7bSMarcel Ziswiler u32 reserved5[93]; /* offset 0x100 - 0x270 */ 34*8c33ba7bSMarcel Ziswiler }; 35*8c33ba7bSMarcel Ziswiler 36*8c33ba7bSMarcel Ziswiler #endif /* _TEGRA20_MC_H_ */ 37